3DIC From the LAnd of the Rising Sun

An exonym (from the greek) is a name for a place that is not used within that place by the local inhabitants. The word “Japan” is an exonym. The Japanese names for “Japan” are Nippon or Nihon. Nippon is used for most official purposes, including on currency. Both Nippon and Nihon literally mean “where the sun originates”, and are often translated as the Land of the Rising Sun.

Probably because of the conference origin [see PFTLE, “    ] Japanese participation in the recent IEEE 3-D IC Conference was significant. I have tried to select several papers which contained significant technical information for us to discuss.

ASET

 The national “Dream Chip”  program [ Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology]  has  2009 funding of 2.3B Yen for 2009. The program and its participants are described in the figures below.

2009 Themes include: (1) R&D on Design Environment technology, (2) R&D on interposer technology, (3) R&D on chip test technology, (4) R&D on cooling and  stacking / bonding technology, (5) R&D on thin wafer technology.

Renesas

As part of the ASET program researchers from Renesas reported on their thinning and dicing technologies in the paper ” Development of Wafer Thinning and Dicing Technology for Thin Wafers”.

The target specification in the NEDO “Dream Chip) Technology” project is to achieve 10±1μm wafer thickness stably after thinning and dicing for 300mm wafer.

Tohoku Univ

Researchers at Tohoku Univ describe micro Cu/SN bumping technology in their paper “10 um Fine Pitch Cu/Sn Micro-bumps for 3-D Super Chip Stack”.

Micro-bumping technologies for under 50 μm pitch using electroplating methods require very fine pitch, uniform height and low resistance. It has difficult to form uniform height of bumps due to current density variations Bump height non uniformity can cause poor metal joining in fine pitch and high density structures. In order to achieve small, fine pitch Cu/Sn bumps, they developed CMOS compatible dry etching processes to remove sputtered Cu/Ta layers without undercut issue.

The figure below shows a fabrication process of fine pitch Cu/Sn micro-bumps. A PECVD TEOS passivation layer is patterned on the metal wiring. Sputtered Ta and Cu layer are deposited as barrier and seed layer and thick resist is patterned for micro-bumps fabrication. 3 μm thick Cu bumps are formed by electroplating and a  2 μm thick Sn layer is deposited by evaporation. The Cu seed layer is clearly removed by Ar plasma sputtering without ant undercut issues. Finally, Ta barrier layer is etched by dry etching method using CF₄ gas.

Conventional electroplated Cu and Sn bumps had difficulty to form uniform height of bumps due to the variation of current density on a wafer. A combination of Cu electroplating and Sn evaporation results in a average bump height of 5 μm and height variation is approximately ±3 % (95%, 2σ),

Evaporated Sn  can provide low resistance bump. We evaluate the difference in resistivity between evaporated Sn layer and electroplated Sn layer. The resistivity of the evaporated Sn layer (10.6 μΩ・cm)  is 29% lower than that of he electroplated Sn layer (15 μΩ・cm). Daisy chains consisting of 10 μm square / 20 μm pitch bumps (1500 in chain) showed Cu/Sn bump resistance of 35 mΩ/bump, which is very low value compared to electroplated Cu/Sn bump.

In order to evaluate the reliability characteristics of micro-joining, thermal cycle test (TCT) were performed at the condition of JEDEC level 2. They  compared the effects of underfill on the reliability. Two samples with high density bumps were bonded at 280 C ; 4.3 mN/bump bonding force, 10 seconds bonding time, Ar plasma cleaning. The table below shows the result of TCT. Even after 1000 cycles, there are no failures without underfill condition.

Univ Tokyo , Toshiba

In their paper “Effect of the Resistance of TSV’s on Performanceof Boost Converter for Low Power 3D SSD with NAND Flash Memories” researchers from Toshiba and the Univ Tokyo investigate how TSV resistance impacts proposed 3D Architectures for SSD’s.

A typical SSD consists of more than 16 NAND flash memories, DRAM’s and a NAND controller. Each NAND flash chip has a charge pump circuit to generate the program voltage of 20V. This is shown in the figure below. When looking at a 3D design layout for such a SSD, the charge pump prevents significant area reduction, VDD scaling, and the fast write-operation of the NAND flash memory. For example, 5 to 10％ area of each NAND flash chip is occupied by the charge pump due to its large capacitance, which raises the cost of SSD. Therefore a new high voltage generation circuit like a boost converter is strongly required to reduce the area, the power, and the write-time of the NAND flash memory.

The figure below also shows a proposed 3-D integrated SSD with NAND flash memories, DRAM’s, NAND controller, and a boost converter. TSV’s connect the boost converter and each NAND chip.

While the parasitic L and C of the TSV’s can be neglected, since they are under 0.03% and 1% of the inductance of the inductor and the output load capacitance, respectively, the parasitic resistance of TSV’s (RTSV) cannot be disregarded.

The authors conclude that Cu TSVs would be more suitable than p-Si TSVs because of lower resistivity (an issue that we have reported on before)[ see PFTLE , “      “, 07/xx/2009]  and that V_out cannot be boosted above 20V when R_TSV is > 210W.

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