Show me the Copper !

………..Ziptronix and CEA Leti reveal details of Direct Bond Copper,  Nanyang’s Cu passivation,  Further Details on Alchimer’s AquiVia……………..

We have previously discussed the industry “rumor”  that  vias middle -copper are having reliability problems [ see PFTLE, “NEC points to  Nickel for Memory TSV“, 07/19/2009; “You Can’t Always Get  What You Want“, 11/24/2008]. Reportedly, the CTE differential combined with the via diameter and aspect ratio, are resulting in TSV’s that  are “popping” during fabrication and  thermal cycling. The name going around for this phenomenon at the recent IEEE 3D IC Conference was “copper pumping“.  Further info on this will be discussed in the next few weeks. I have also arranged for Paul Ho, U Texas - Austin, who many of you know as an integral part of the copper low K technology developments  a decade plus ago, to present his latest 3D IC modeling data at the RTI 3D ASIP conference coming up in December. Anyway, despite this undercurrent of uncertainty about the “reliability windows” for Cu TSV, it is clear that the industry still desires any eventual 3D TSV processes to be Cu based due both to its conductivity and its compatibility with IC fabs.

Lets look at what was presented about Cu technology at the recent  IEEE 3D Conference.

Ziptronix DBI with Copper

When Ziptronix first revealed details of their DBI (Direct Bond Interconnect) process a year ago [ PFTLE, “Opening the Kimono, Ziptronix Gives Details on DBI Process“, 10/14/2008]  we saw details on Ni as the DBI metal and got assurances that the process could be practiced with Cu [PFTLE, “Fisk, Buckner and Pasta in the North End“, 12/31/2008]. Copper DBI doubters said “Show me the copper !“. At the IEEE 3D IC Conference we were, in fact, shown the first Cu data using the DBI process.

In the Cu DBI® process arrays of barrier layer lined Cu damascene filled vias in a coplanar silicon oxide matrix are first direct oxide bonded at room temperature and then post bond annealed at 125 °C  to make 3D electrical interconnections. It was pointed out that this low thermal budget was an advantage, for example certain types of 3D memory and heterogeneous integration, that might require a thermal budget less than the normally required 1+ hr 350 °C required for thermo compression bonding.

While cross sections showed no grain boundary mixing at the bond interface (which would be expected for a fusion bonded interface), CTO Enquist indicated that these are reliable electrical bonds with contact resistance of 50 mW and contact resistivity of ) 0.5 W - µm². They performed Temperature Cycling (-65°C - 175°C, 1000 cycles) and HAST (130°C, 85% RH, 33psi, 144 hours) with good results at 125. 150 and 350 °C. Published  DBI processes are compared in the table below.

* (Ni TSV announced by NEC but not in prod)

** ( or better subject to alignment tool accuracy)

Although the barrier layer protects the SiO₂ from Cu in the via, the slight misalignment shown in the figure below results in an exposed  Cu / SiO₂ interface and leads to questions of Cu migration and reliability issues. When questioned about this later Enquist responded “…we have a DBI process variant that eliminates this issue. We will be presenting this at the RTI 3D Conference in Burlingame in December. This is why we presented the Ni DBI process first, it shows good reliability without requiring any barrier lining of the via or the bond interface”

CEA Leti Details Direct Bond Cu Vias Last Process

CEA Leti presented details on their latest direct bond copper process. We have discussed the Leti direct copper bonding previously [ see PFTLE, “Fisk, Buckner and pasta on the North End“, 12/31/2008; “The French Connection ….”, 07/26/2009 ]  In this die-to wafer (D2W) process Leti first does a face-to-face (F2F) Cu-Cu direct bonding of KGD to a processed wafer. The surfaces are prepared for bonding by CMP and “chemical steps ” to achieve “high hydrophilic character”. The die on the populated wafer are then thinned and the area between the dies are then filled in with “low stress high deposition rate oxide” to achieve a flat smooth surface. TSV are then fabricated through the thinned Si to the back of the bonding pads to make the connections to the next layer. This is shown in the process sequence below.

Leti did not show a liner/barrier layer around the Cu but discussed that they were working on that. As is the case with the DBI process (shown above) any miss alignment of the copper studs will result in a copper - SiO₂ interface which will cause copper migration / reliability concerns.I’m sure we’ll see solutions for this in their next presentation.

Nanyang  -  Monolayer Passivation for Direct Bond Copper

As we have discussed in the past, some kind of passivation is necessary to prevent oxidation before and during a direct bond copper process [see PFTLE, “Fisk, Buckner and pasta on the North End“, 12/31/2008]. Researchers from Nanyang Technical Univ and Chartered Semiconductor presented their results on using hexane thiol as such a passivation. They have found that this material when coated on a freshly cleaned Cu surface deposits a monolayer (please lets NOT call it a nano layer)  on the surface which can be observed as changing the surface from hydrophilic to hydrophobic. They also examined the desorption of the material which appears to be complete by 200 °C. They have concluded that good bond formation must be immediately proceeded by thermal removal of the passivation material.   You can easily conceive how this would be implemented into a DBC (direct bond copper) process.

Alchimer Gives Further Details on Copper Based AquiVia Process

Alchimer CTO Claudio Truzzi gave an update on the only  complete wet  processing solution for copper TSV filling currently available - “AquiVia”. We have discussed the Alchimer technology before [ PFTLE, “Start Ups with a Future“, 06/20/2009 and “The French Connection…“, 07/25/2009]. The only part of this innovative technology that still appeared “incomplete” was full information on the electrografted insulator.

While we are still awaiting disclosure of the chemical composition of this polymeric material, this presentation certainly shared all the information we could want to know about its properties. Truzzi reports that a specific organic precursor is used both to form a first primer grafted layer and to initiate the polymerization of the vinyl monomer present in solution. They are simply dissolved in acidic aqueous solution and placed in a electrochemical cell. Insulator film properties are given in the figures and tables below.

The CTE and Dk are very reasonable. The thickness uniformity, BV and leakage current are excellent.

I have been especially interested in the thermal stability of the polymer insulator, since previous results were reported as “ramped TGA” data which are notorious for exaggerating the thermal stability of polymeric materials. Below is the new Alchimer data which has been collected isothermally and shows rock solid stability at 350 °C.

Deposition of the NiB barrier layer is preceded by a simple Pd catalyzed activation similar to what is done for electroless copper deposition.

Surface CMP is made easier due to the lower overburden generated by the electrografting technique vs typical PVD or CVD depositions.

While one may still question their COO results (which show significant cost savings by their process), it is obvious, without crunching the numbers, that a completely wet filling process must have a significant equipment cost savings potential.

All the data now seems to be in place. It appears the AquiVia process is ready for scale up. PFTLE will be keeping an eye on this intriguing process.

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