The 4 Horsemen of 3D IC

The biblical Four Horsemen of the Apocalypse are often referred to as “war, famine, pestilence and death,” things that can figuratively and literally bring us to our knees or worse — put us 6 feet under. For several years now I have finished off 3D IC courses with a listing  of the areas that can still bring 3D technology to its knees: (1) design; (2) thermal management; (3) test; and (4) cost reduction. When it comes to 3D IC these are the Four Horsemen, so to speak.

The initial focus of a new microelectronics technology is always: (1) why should we do it [what are the drivers] and (2) how can we do it [what are the processing options]. But for 3D IC  it is not enough to have positive responses to these two questions, the Four Horsemen must be dealt with in order for 3D IC to have major impact.

In this blog we’ll take a look at the pale horse called Design. We’ll be updating the other horsemen periodically as time permits.

Early on, R3Logic was the only company vocal about 3D IC design. For instance, in the fall of 2007 Cadence CTO Ted Vucurevich indicated that they would be developing 3D tools sets “…once it becomes clear that the market intends on going in this direction (PFTLE, “3D Discussions in the Valley … Continued,” Nov. 4, 2007).”

Early in 2008, at an IMEC research review,  a panel of design experts called on Cadence, Mentor Graphics and Synopsys to become more involved with 3D design products (PFTLE, “IMEC Arrives in Hsinchu and Other 3D IC News,” Feb. 26, 2008).

Thankfully, things have changed in 2009.  First Cadence (PFTLE, “Deep in the Heart of Texas,” April 4, 2009) and then Synopsys (PFTLE, “MCA Delivers 3D Brightspot at Semicon,” July 31, 2009) have indicated  significant interest in 3D from their customer base and therefore increased interest on their part. This increased activity in the design area was clear at the recent SF IEEE meeting as evidenced by the following selected papers.

R3 Logic

Lisa McIlrath of R3Logic gave an interesting status review of 3D design in her paper, “Design Tools for the 3-D Roadmap.” Her theme was that 3D will be integrated into products because of economics, not the availability of adequate EDA tools, but that the speed at which progress towards this end will be made will be a function of how quickly both system architects and physical designers are able to manage the new complexities that 3D integration brings.

She contends that the progress that has been made to date in designing 3D has largely been done without any special tools. “Over the last decade and a half, researchers in a handful of institutions around the world have produced several 3D system prototypes using standard 2D tools augmented by scripts,” she said.

She proposes that two main features are required in a true 3D tool, without which it is very difficult to automate a complete design flow. These are: 3D Technology Independence and 3D Hierarchy management. 3D Technology Independence means the ability to separate the details of the 3D stacking or integration process from those of the separate 2D wafer process technologies. A 3D Hierarchy is one in which parent-child relationships can exist between cells on different wafer tiers, possibly with different technologies, as well as between those on the same 2D wafer tier. A 3D tool must be able to maintain dependencies between functional blocks on different tiers in order to permit effective co-design of the entire system.

Two areas in particular are on the critical path for volume production of 3D TSV integrated circuits: Design for Manufacturing (DFM) and Design for Test (DFT).She offered the following of a 3D EDA roadmap. By 2010 /11, architectural evaluation engines will need to be available to break out of incremental, evolutionary growth. At some point in the near future, and hopefully before 2013, there will be standards in place for test and 3D IP component compatibility.

RPI

It has been well recognized by the computer architecture community stacking multiple high-capacity DRAM tiers with one processor tier and enabling massive inter-die interconnect bandwidth, 3D processor-DRAM integrated systems can achieve drastically reduced memory access latency and increased memory access bandwidth. The processor tier must directly attach to the heat spreader and heat sink. Hence, the DRAM tiers should be placed between the package substrate and the processor tier as shown in the figure below. As a result, a certain number of through-silicon vias (TSVs) must go through the stacked DRAM tiers to deliver a large amount of current and all the I/O signals from the package to the processor tier(s). Clearly, those through-DRAM TSVs will inevitably affect the DRAM design and incur DRAM storage capacity degradation.

Researchers at RPI in their paper entitled “Impacts of Through DRAM Vias in 3D Processor DRAM Integrated Systems” described  a through-DRAM power and signal TSV allocation strategy that can fit into the regular DRAM structure. They propose a uniformly distributed power TSV network design approach, which makes the fabrication of through-DRAM power TSVs not interfere with the DRAM design itself.

Besides TSVs connecting the processor die and DRAM dies, a large amount of TSVs are used to connect power and signal I/O pins between the package and the processor die, which must go through all the stacked DRAM dies and are referred to as through-DRAM TSVs.

Since each signal TSV can use the minimal allowable TSV size (e.g., a few µm of diameter) and microprocessors typically have a few hundred signal I/Os, through-DRAM signal TSVs tend to occupy a very small area on DRAM dies. This strategy can readily decouple the design of the DRAM dies and the microprocessor die, i.e., we can allocate a large enough number of through-DRAM signal TSVs on DRAM dies so that the same 3D DRAM can serve for different microprocessor dies with different amounts of signal I/Os. In comparison, through-DRAM power TSVs could have a much bigger impact and result in nontrivial system design trade-offs. To reduce such power consumption overhead, they propose reducing the resistance of through-DRAM power TSVs, by increasing the size of those TSVs.

To readily accommodate the fabrication of a large amount of through-DRAM power TSVs (e.g., thousands or tens of thousands), they propose to arrange a regular power TSV network around those individual DRAM sub-arrays.

KTH Royal Institute of Technology

Researchers at the KTH in Sweden have examined the performance of processor-memory architectures formed within a 3D structure with NOC (network-on-chip) architecture as a communication backbone, in their paper “3-D Memory Organization and Performance Analysis for Multiprocessor Network-on-chip Architecture.”

The traditional processor-memory organization is set based on the assumption that there is inherent off-chip memory storage such as HDD. In order to access this off-chip memory, two important factors are considered: (1) the memory access time is relatively long compared to the active response demanded by the processor, and (2) the energy required to access off-chip memory through the chip bond-wires, printed circuit board (PCB) tracks, cables and mechanical. To overcome these challenges, several methods of memory hierarchy have been examined. In general the processor block is connected to the main memory and then to the HDD with Bus as a communication backbone. A cache block is placed usually close to the processor to shorten the memory access time and save energy.

KTH compares several memory architectures with colorful names such as “dance-hall,” “sandwich” and “terminal” based on parameters such as cache coherency, power consumption, off-chip I/O access, thermal stress management, cost and performance.

Two important conclusions were reached based on their results: (1) The on-chip network latency variation is a fraction and insignificant compared to the  number of processors running in parallel to share the memory blocks. (This means the total access time will be determined by the flash technology implemented in the memory blocks. The network delay, due to planar wires, TSV and switch circuitry combined is not significant, if one uses NOC as a means of communication between the processors and the memory blocks.) (2) In terms of performance, locality improves the performance of some architecture while degrading others. In general, a high-level scalability and parallelism can be gained by implementing 3D memory based on NOC architectures.

Cadence

In their paper “IC-Package Co-design and Analysis for 3-D ICs,” Cadence discusses five key ingredients necessary for the successful design of 3D IC, namely:

- Logical system-level integration to connect the system of ICs and packages, including support of layout-vs-schematic (LVS) checks
- Physical co-design across IC and package boundaries through the sharing of component abstracts and cross-fabric functionality
- Timing, power, and thermal-based design of the 3D-IC system in context of the package
- Package-aware system simulation of 3D-IC circuitry
- Management of physical and logical engineering change orders

There were many more excellent design papers included in the conference. Get a copy of the conference CD to read these and the others in further depth.

For more updates from the IEEE 3D-IC Conference stay linked to PFTLE………