Optimism vs Reality ; Semantics or Lost in Translation ??
Many of the non USA PFTLE readers from around the globe that I meet at 3-D IC conferences bring up that “every few blogs you start off with material that we really don’t understand….what is this for ?” I try to explain that these are blogs and while I try to keep the technical content at a very high level, I also take the opportunity, every few blogs, to give my opinion on how and why things are done. I compare these to a Dennis Miller “rant” [ “this is just my opinion and I could be wrong” - Dennis Miller] but I understand that many of you outside the US don’t really know who Dennis Miller, a US TV personality, is. A rant or tirade is defined as “a bombastic extravagant speech” usually criticizing something. Anyway my apologies if these don’t make sense to all of you, but all of them do contain a point that I’m trying to make.
For instance, as I have been pouring over the final papers from the recent IEEE 3-D meeting in SF it struck me that without the program I could not tell which papers were given orally and which were in the poster session. Some of you, that are younger and less experienced, often ask “why wasn’t my paper selected for oral presentation ?” Truth be told no one can really tell what the quality of a presentation is going to be from a 50 word abstract. When you are sitting in the paper selection meetings you go partially on what is described and partially on the reputation of the main author (30/70) …this may not be fair, but this is reality. My suggestion is that if you know that your not looked upon as a “key player” in the field and do not personally know the paper selection committee members, put as much information as possible in these abstracts. Forget the introductory material and cram the abstracts with data. If figures and tables are allowed, the more the better. Realize what your competing against and accept reality. If I know someone as a colleague, and they have given many papers through the years, and they are always excellent quality, they can make it with a mediocre abstract, but you cannot.
Anyway, I’m certainly man enough to admit that several of the papers that I voted to be presented as a poster at the recent IEEE 3D meeting were excellent quality and several of the papers that I voted to be presented orally were not. One thing that we are doing correctly, in recent times, is allowing poster papers to be submitted as full written papers to the proceedings. In the end, these are what will be remembered about your work - so really focus on making the manuscripts as good as possible. What I will relay to you in the next few blogs, about the important information from the IEEE 3-D IC Conference, will make no distinction between posters and orals, the way it should be !
Now, back to the title of this blog. I thought I would first cover material which updates topics that we have spoken about in the past, so here we go.
Elpida DRAM Product Announcement
Memory has always been viewed as the key application for this 3D TSV market whether it be stacked memory or memory stacked with logic. First there were indications that NAND was poised to use 3D TSV technology first [PFTLE, “3D Discussions in the Valley Continue..”, 11/04/2007 ] but that never really made any sense from a cost perspective. The first solid information we got on the timing for the memory market came in the spring of 2008 [ PFTLE, “Road Trip Revelations”, 5/18/2008] which indicated that we would see DRAM use 3D TSV stacking at the 1333 - 1600 Mbps DDR3 generations. As real product prototypes have started to appear ( 8 Gb DDR3 DRAM) from Samsung [PFTLE, “3D IC at the 2009 ISSCC contd.”, 02/25/2009] and more recently Elpida [PFTLE, “Ginko Biloba”, 09/12/2009] this timing data appears to be holding up.
The recent Elpida press announcement indicated that “…Elpida has installed a manufacturing line for TSV at the Hiroshima Plant…. ” and that “..sample shipments of the 8-Gigabit TSV DRAM are scheduled to start before the end of 2009″ This was quickly picked up by several marketing firms and many news and blog web spots as meaning that Elpida would be “shipping” 3D TSV stacked DRAM in 2009 whereas my interpretation [ PFTLE, “Ginko Biloba”, 09/12/2009] was that a pilot line had been installed and product sampling would occur soon. Is this semantics? or was their something “lost in translation” ?
Having had to actually make and ship things in my career I make very clear distinctions between sampling and shipping. This announcement shows great evolutionary progress but “shipping” will occur from a qualified line on a qualified process running a qualified product and none of that, I can assure you, will be occurring in 2009 for DRAM. My guess, based on the recent announcements, is another 18 months before we can all celebrate. During a panel discussion at the recent IEEE 3D meeting, one of the panel members recited the headline that “…as we all know Elpida has a line in place and will be shipping 3D DRAM in 2009″ when I gave my perspective (as detailed above) and asked Kada-san from Japans ASET consortium (sitting next to me) if that was correct, he responded “correct”. I was later told by other Japanese “players” in attendance that my interpretation was correct. Again, this announcement is a great thing, but lets keep our optimism balanced with reality.
CEA Leti / ST Micro Set Top Box Product Demonstrator
We have previously applauded the ST Micro demonstrator which stacked 45 nm and 130 nm die [ PFTLE, “From the home of Fellini - 3D Integration”, 07/09/2009 ] . Now David Henry and his fellow CEA Leti colleagues have released more details on this joint program with ST Micro. This demonstrator is actually for a set top box application. The 45 nm top die is thinned to 180 um and Cu pillar/solder interconnect is on 50 um pitch. The bottom, 130 nm wafer (called the “active interposer”) is thinned down to 120 um. TSV are 60 um diameter resulting in a 2:1 aspect ratio. Backside connection uses tall Cu pillars and Sn/Cu/Ag solder. The process flow is shown in the figure below.
Thinning is accomplished by temporary bonding using the Brewer 10.10 temporary bonding product which sets a subsequent process temp limit of 300 °C . Debonding is achieved by the “slide-off” process at 150 -220 °C. TEOS PECVD is used as insulation with a measured conformality (top to bottom) reported as 31%.
67% of the chips had a resistance below 20 mW per via. 80% of the chips show a resistance below 50 mW. They observed a small edge / center variation which reportedly was resolved by changing the DRIE tool and using an electrostatic chuck instead of mechanical chuck.
The current leakage values (10V) were comprised between 10-6 and 10-5 A . For these applications they report that they need 10-8 and 10-7 A. Since dielectric thickness was 0.3 / 0.5µm they are looking at increasing the dielectric thickness in order to improve the current losses and the TSV parasitic capacitance.
Aviza
In the past we have discussed Zycubes comments that CIS needed < 180 °C insulation deposition temperature due to the thermal stability of the lenses [ PFTLE, “Rest of the Best at 3D ASIP”, 12/03/2008] and color filters [ PFTLE, “3D Practitioners Assemble at Ft McDowell”, 03/23/2008]. However, since these devices are being operated at 3.3V, lower density and thus BV (breakdown voltage) oxides were considered acceptable. In the 12/03/2008 blog we also indicated that Tegal (who had acquired the Alcatel Micro machining Systems Division ) reported that deposition of SiO2 was possible at 150 °C yielding a BV of 7.5 MV/cm. It has also been clear that such low temperature oxide deposition will be applicable to future DRAM generations which are also temperature sensitive.
Aviza, who announced a corporate restructuring in April, has been focusing on 3D IC unit process operations including Si etch, SiO2 deposition, SiO2 etch and barrier and seed deposition by PVD and ionized PVD. These operations are all included in their Versalis fxP cluster tool. At the recent IEEE 3D IC Conference they shared details on their low temp CVD SiO2 deposition process.
The SiO2 deposition process was optimized to maximize via conformality while providing the required electrical performance (low electrical leakage current and high breakdown voltage) and stability over time. The figure below shows how the via sidewall coverage varies through the depth of 4:1 aspect ratio vias for both silane and TEOS-based PECVD processes with 200°C deposition temperature. The TEOS process clearly gives increased conformality compared to the silane-based process (similar to what has been reported by many other researchers).
Low temperature PECVD films are typically of low density and have excessively high leakage current, making them unusable in TSV applications where excellent electrical isolation between via metallization and the silicon substrate is required.
The figure below compares the electrical leakage current density vs applied electric field strength, measured on MIS structures with Aviza low temperature PE-TEOS as the dielectric at deposition temperatures of 100°C, 125°C and 150°C. Films deposited at 100°C and 125°C have unacceptable leakage currents, but films deposited at 150°C and above have significantly lower leakage currents and the leakage does not drift over time.
The Table below summarizes the properties of Aviza’s 200 °C PECVD TEOS based SiO2 films.
More updates coming in a few days……..For all the latest on 3D IC and advanced packaging stay linked to Perspectives From the Leading Edge (PFTLE)………….
