3D IC in the City by the Bay

This is the 100th edition of Perspectives From the Leading Edge. When I started this blog, many doubted that there would be enough information on 3D IC to do weekly coverage on this subject. To the contrary, as the field has expanded over the last 2 years, I have been deluged with information, and the real job has been filtering “the wheat from the chaff”. I’d like to thank all of you for your continued readership.

The next few blogs will cover the activities at the recent IEEE 3D IC conference in San Francisco. This meeting was set up through IEEE CPMT Society (Components, Packaging and Manufacturing) to be the key global technical meeting for this evolving technology. This conference combined the previous ASET and IEEE EDS Society sponsored International 3D System Integration Conference, held in Tokyo in 2007 & 2008 and the IEEE CPMT sponsored 3D System Integration Conference held in 2005 & 2007 in Munich. The new, combined Conference will rotate to Munich in 2010 and Tokyo in 2011 before returning to the US.

The September SF meeting was a great success with 210 attendees ( ~50% from US, ~25% from Asia and ~25% from Europe) sharing information with their global colleagues. The picture below shows many of the organizing committee members who were present at the meeting. There were 50 oral presentations and 37 posters. The Sunday tutorial drew 60 students.

[Back row] Xie (Penn State),  van Doremalen (Philips), Garrou (MCNC), Tanaka (Univ Tokyo), Patti (Tezzaron), Schaper (Univ Arkansas), Enquist (Ziptronix), Morrow (Intel), Keast (MIT LL)

[front row] Motoyoshi (Zycube), Aoyagi (AIST), Beyne (IMEC), Koyanagi (Tohoku Univ),  Yamada (IBM Japan), Kada (ASET) , Lu (RPI), Franzon (NC State Univ), Patel (Altera)

The organizing committee voted the following presentation Best Paper of the Conference.

Lincoln Labs

MIT’s Lincoln Lab reported on their DARPA sponsored 3D integration process to combine Si readout circuits with InGaAs photodetectors for short-wavelength infrared (SWIR) imagers. The process oxide bonded SOI process was run on 150 mm InP and Si wafers.

Using low-temperature oxide-to oxide wafer-bonding technique, the SOI wafer with readout circuits was bonded face-to-face to the InP wafer containing diode arrays. The alignment accuracy was better than 1 μm, and the highest temperature in this bonding process was 175ºC. The Si circuit on top of the InP substrate is mostly oxide and metal layers with scattered SOI islands for FETs. The complete removal of Si handle wafer can alleviate stress issues created by the thermal mismatch between InP and Si.

The 1024 x 1024 array of 8 um pixels each has one 3D via at each pixelfor access to one complete Si readout circuit for each InP/InGaAs PIN diode.

They examined the MOSFET performance before and after integration and found no apparent degradation caused by the 3D process as shown in the figure below.

For all the latest on 3D IC and advanced packaging stay linked to Prespectives From the Leading Edge [PFTLE] ………………..