Ginkgo Biloba

For a while now I’ve thought that if I were running a corporate 3D IC memory program my project code name would be “Ginkgo Biloba” since the Ginkgo has many alleged nootropic (memory enhancing) properties.

As a follower of PFTLE, you’re well aware that when it comes to 3D IC the CMOS image sensor (CIS) may have come first, but it is the huge memory market that everyone is waiting for.

PFTLE has not supported the prognostications that 3D memory would happen quickly (i.e. reports that 9 memory suppliers would be in commercial production by 2010 — see PFTLE, “A Rose by Any Other Name Is Not 3D IC Integration,” 11/20/2007), or predictions that 20% of the DRAM market and 30% of the flash market would be manufactured with 3D IC technology in 2012 (see PFTLE, “3D Discussions in the Valley… Continued,” 11/04/2007).

3D memory surely will happen, just not that quickly. We’ll know it’s happening when the equipment is in place, the production lines are identified, the processes are qualified, reliability data is released, and product starts shipping. That, I’m sure we can all agree, has not happened yet. Be assured, we will let you know when it does.

Although Samsung showed us 3D prototypes in 2006 (see PFTLE, “3D IC Integration: Rumors and Ruminations,” 02/08/2008), we are still awaiting any announcement of commercial production. Likewise, Micron has indicated that memory could not advance without 3D IC stacking (see PFTLE, “Road Trip Revelations,” 05/18/2008), but has made no product announcements. Although Toshiba was the first to commercialize TSV in image sensors (see PFTLE, “Imaging Chips With TSV Announced for Commercialization,” 10/27/2007), there has been no mention of 3D memory products… yet.

What PFTLE believes in terms of commercialization timing is what we have shared about DDR memory (see PFTLE, “TSMC Roadmap, DRAM Timing and Sematech Highlights,” 10/27/2008), which is that TSV stacking will be REQUIRED when DDR3 DRAM is implemented at 1600Mbps. These exact same figures appeared again when Samsung showed their 8GB DDR3 DRAM earlier this year at ISSCC (see PFTLE, “3D IC at the 2009 ISSCC Contd.,” 02/25/2009).

We also know 3D IC memory is coming because both Intel (see PFTLE, “ASET Drives 3D Integration Workshop in Tokyo,” 06/21/2008) and IBM (see PFTLE, “SMTA 3D Meeting in Research Triangle Park,” 05/10/2008) have told us that multicore processors cannot continue to progress without 3D stacked memory to give low latency, wide bandwidth access to data. … We just don’t  know exactly when.

As you probably saw in the Semiconductor International feature story last week, Elpida announced the development of a Cu-TSV 8-Gigabit DRAM technology. This is important for two very separate reasons:

(1) It verifies earlier reports from NEC that vias first, polysilicon conductor technology, which Elpida had reported on previously, is not moving forward (see PFTLE, “NEC Points to Nickel for Memory 3D TSV,” 07/19/2009).

(2) They are describing very specific prototypes that customers will be able to get in late 2009 and early 2010, and indicate that manufacturing is in the near future.

Sample shipments of an 8-Gigabit DDR3 SDRAM are reportedly scheduled to start before the end of 2009 and sampling of a 16-Gigabit product is scheduled to begin by mid-2010. PFTLE reads this as production ~18 months later.

Elpida indicates that in preparation for manufacturing, they have installed a “manufacturing line for TSV at the Hiroshima plant, and will make use of Akita Elpida’s package processing to conduct full-scale production in Japan.” The Hiroshima plant has 300 mm capacity (as does its Taiwan-based joint venture, Rexchip Electronics). It is not clear from the information released thus far that this is a full, balanced manufacturing line, and bets here are that it is a low-volume prototype line, but this is still a significant milestone for this evolving industry. It would be interesting to know whether the line or the process have been qualified. My guess would be … not yet.

The 8-Gigabit, 1.3 mm high DDR3 SDRAM operates at 1,600Mbps (the magic number) and consists of eight 1-Gigabit DDR3 SDRAM chips and an interface chip as shown in the figure below.  There reportedly are 1030 connections between the core layers. This 8-Gigabit DRAM reportedly uses one-fourth of the standby power compared with multi-chip package and PoP solutions.

There is no indication as to the process used to fabricate these prototype parts, but what’s being shown looks a lot like the Tezzaron DRAM designs of stacked memory cells with an interface chip (see figure below).

Elpida reports that application of such 3D IC products can reduce power consumption of servers, data centers and other high-capacity memory systems and reports that potential applications include:

- Ultra high-density DRAM modules for use in supercomputers and servers
- DRAM/logic chip stacks to enable high-performance mobile devices
- High-end graphics chips for use in high-performance digital consumer electronics and game consoles

We are getting closer, so you should  expect this announcement to push others to make further announcements as we saw, and explained, for CIS (see PFTLE, “…On Mechanical Bulls, Rollercoasters and CIS With TSV,” 09/26/2008).

For all the latest on 3D IC and advanced packaging, stay linked to PFTLE…………