Suss Microtec Thin Wafer Processing 3D IC Workshop
Last but not least in my review of the 3D activities at 2009 Semicon West is the Suss MicroTec sponsored “Thin Wafer Processing for 3D TSV Applications Workshop” that was held on July 15th. Speakers and chairs are shown in the group photo below.
[L to R: Swinnen, Bair, Sullivan, Keigler, Bourke, Milasinsic, Richter, PFTLE, Dronnen]
Scott Sullivan - Disco Hi Tec
From Disco’s perspective Scott listed the following as issues that were pretty much “under control” :
- Grinding
- Wafer Breakage
- Handling
and the following as areas that still needed work:
- Thinning & Exposure
- Post Height Variation
- Post Pitch Variation
- Transferring of Exposed Post Wafers
- Cleaning
- Copper Contamination
Wafer chipping is avoided by edge trimming as shown in the figure below.
Backside post exposure is currently a major issue. One can grind down to expose the posts or stop short of the posts and remove the remaining silicon selectively, to expose the posts. Process A tends to crack the insulating layer and smear the Cu and process B, once further Si is removed, tends to reveal uneven post heights. The Disco solution is to surface plane the uneven post heights as shown below.
Blake Dronnen - 3M Wafer Support System
In an earlier PFTLE report [SUSS MicroTec Bonders for Temporary and Permanent 3D Bonding Solutions, 06/24/2009] we detailed how SUSS MicroTec and 3M have announced an agreement where Suss offers 3M’s temporary bonding process as part of their new SUSS 300 mm bonder line and the UV curable adhesive and light-to-heat conversion (LTHC) layer used in the laser debond process will still be sold through 3M.
The performance of their UV curable temporary adhesives are shown below.
Their light-to-heat conversion layer has the following attributes:
Chris Milasinsic - DuPont Electronic Materials
Like many of the other major chemical suppliers DuPont is aligning it’s product lines against the expected 3D IC market as shown in the fig below.
Their proposed process sequence using PI 3007 as a temporary adhesive and PI 7002 as a permanent adhesive are shown in the figure below. Attach is by Cu/Sn eutectic. The handle and temporary adhesive are removed by laser ablation / solvent. The key to this process is that the thinned wafer / die are never handled in thinned form.
Hans Richter - Thin Materials AG
In the Thin Materials temporary bonding process the wafers are first coated with a thin ( few hundred nm) proprietary release layer and subsequently bonded with silicone elastomer at 180 °C. Wafer thinning down to 50 um and heat resistance above 250C has been documented After thinning and attachment to the dicing frame the carrier substrate is reportedly lifted off at room temp and the remains of the release layer are rinsed off with a simple hydrocarbon.
Arthur Kiegler Nexx
Arthur made the very interesting point that if an electrostatic chuck is being used to hold a wafer, it can be used to draw heat out of the system. The increase in throughput that this allows (when trying to hold the temperature at or below 150 °C) is shown below. This requires a conductive substrate, i.e silicon not glass. Arthur asks the interesting question “Can glass carriers have a conductive layer added to them ? ”
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