Road Trip Revelations

We can all remember the great John
Belushi character in Animal House who, when things got a little
dull called for a “…ROAD TRIP” Well just as things
began to get a little slow on the 3D news front a cross country
road trip last week certainly changed all that.

Back in my blog on 08-26-07
“3D Equipment and Materials Vendors
Consortium” I informed you that a second
equipment/materials consortium was in the process of forming with
the same basic goals and functions as EMC-3D. Ends up they would
rather not be seen as a “consortium” ( legal
implications I assume) so I won’t call them that, but as
I’ve said before “…a rose by any other name
…you know the rest”. This “loosely affiliated
group” is spearheaded by Suss Microtec, STS and Nexx and you
can find details of what they are doing on their web page http://www.3dintegration.org

Their first 2008 3D road trip just
ended that covered RTP, Dallas and San Jose. Some very interesting
new 3D news came up on the tour that I will share with you first
here first on Perspectives from the Leading Edge and later
on a full writeup for the Semi Int print edition.

The materials suppliers that went on
tour included Enthone, AZ, MicroChem, DuPont, and RHEM (Rohm &
Hass Electronic Materials). We were joined at several of the stops
by presentations from Ziptronix, Amkor, Micron, RTI, and
Tezzaron.

We’ll start with the
presentation by Micron. To say that Micron has been in
“stealth mode” on their 3D program would be an
understatement. In Aug 2006 they announced their
“Osmium” technology which included WLP and 3D and we
have seen little additional details since. During Microns recent
spin out of Aptina they indicated that they would be following the
lead of other CMOS image sensor suppliers and building their
devices with TSV. Now, finally thanks to Micron’s Kyle Kirby,
we are getting a clearer picture of their memory plans.

Kirby indicated that Micron’s
needs for 3D and TSV are not only for Aptina but also for stacked
DRAM, memory on Processor and NAND. Kirby indicated that the
industry as a whole and Micron specifically would be moving to 3D
IC Integration with TSV out of necessity in order to keep up with
required device performance in the future. As we have been saying
here for awhile, the DDR3 and DDR4 requirements of 1333+ and 1600+
Mbps speeds will require 3D TSV device packaging.

Kirby indicated that performance,
power, form factor, thermal and cost considerations will drive
future stacked DRAM designs from current DDP/QDP to 3D Integration
TSV type technologies. As can be seen in the Micron slide below,
they believe that DDR3 and DDR4 will make up a large proportion of
DRAM by the 2012 – 2014 timeframe

The Micron chart below also
indicates that they perceive that TSV will get smaller, pitch will
get tighter and layers will get thinner as this technology
commercially evolves.

We also got a glimpse at what the
I/O requirements will be for memory die stacked through their
current pad configurations. We see below that a 4 layer stack will
require 3 extra I/O per current pad for chip select functions.

…………………..For more
information from the 3D road trip stay linked to Perspectives
From the Leading Edge………………..