Some things need repeating....

September 29, 2007

There have been a couple of
interesting 3D integration related announcements in the past two
weeks. They have been covered, as isolated events, on the
Semiconductor International main web page when they
happened, but its probably not a bad idea to look at them again in
context of what they mean to the whole “Chips Going Vertical”
theme.

The first was the
announcement at the SIA meeting, in NYC, mid
September. The main news was that “…the reality is that our
ability to shrink the size of the transistor will be limited by
physics sometime within the next 10 to 15 years. The industry is
working on the transition from the transistor to entirely new
device structures”. They continued that these entirely new
devices such as carbon nanotubes, spintronics or molecular switches
would not be ready for prime time production for 10 – 15
years but not to worry because in the interim we will see
“….both evolutionary and revolutionary changes …. new
assembly methods that will enable continuation of progress for
decades to come” Specifically called out as the technology
coming to the rescue was 3D IC
integration

The second event was the
announcement on Sept 18^th in Taiwan by Ho-Ming
Tong, chief R&D officer for ASE, that ASE was
indeed working on 3D integration TSV and anticipated
production during the 2008 – 2011 time frame coincident
with the startup of the 45 nm node. He saw the first applications
for ASE being super thin memory stacks assembled in SiPs
for the latest, thinnest mobile phones and other mobile
appliances. If we look further at this announcement we find that in
May 2007 Aviza Technology announced it had received a
“multiple system order” for its Omega i2L etch system
from ASE which would “…use the system to develop TSV
processing capability”. We already have seen announcements
from STATS ChipPAC in May 2007 announced it had
purchased the Shott Glass CMOS imaging chip packaging facility in
Singapore and would be “…developing the next-generation
technologies including through-silicon vias (TSV),
microbump bonding methods for 3D die, silicon substrate-based
system-in-package solutions…” at this site.
Amkor announced in July that they
had signed a collaboration agreement with IMEC for 3D
integration technology. So, it is obvious that the big boys in
Assembly & Packaging are getting ready but what about the IC
Foundries ???

If you read any of the literature I
pointed you towards in previous blogs, you know that the easiest
way to enter the 3D integration era (non memory) would be for the
IC foundries to offer FEOL or BEOL production of the required TSV
in the IC that you ordered. June 2007 saw the announcement from
Tezzaron and Chartered that Chartered would be
scaling up Tezzarons BEOL TSV process. TSMC,
traditionally closed mouth about their future technical plans, has
expectedly been tight lipped about 3D integration when asked (and
they have been asked) . A closer look, however,
reveals a plating joint development program announced
between TSMC and Nexx in March of this year. If you read
closely, Nexx reveals the 300 mm tool would be installed in Fab 7
in Hsinchu and would be used to develop TSV
technology. Further detective work reveals that TSMC is a
member of IMEC’s core program on sub 32 nm CMOS (along with
Infineon, Intel, Micron, NXP, Panasonic, Samsung, TI
and ST Micro) . So, although we can’t say they are
about to announce production plans, we can say they are probably
taking a serious look at 3D integration as I blog…..