3D Practitioners Assemble at Ft McDowell

The casino was second rate, the
food in the casino was third rate but the information on 3D IC
integration was priceless. The IMAPS Device Packaging
Conference, attended by well over 500 professionals, is now
history. In the next few blogs I will go over some of the
significant information gleaned from the presentations and the side
conversations in the hall ways.

First lets start with CIS (CMOS
Image Sensor) packaging. If you’ve been keeping up with these
blogs you know that Toshiba, Oki-Zycube and most recently ST Micro
have announced 2008 production capacity for this wafer level
packaging technology which uses backside TSV. In my last blog I
pointed out that ST Micro is already working to apply this
technology to stacked die products where memory would be added to a
media processor.

New Information on the ST
Micro CIS technology

Indications are that ST Micro is
using their normal redistribution technology to do backside wafer
processing for their miniature CIS devices (Cu/BCB). While this is
clearly the easiest way to get into production for these one level
devices, it does bring to question whether thermal processing
issues will allow this backside technology to be used for the next
generation stacked devices. We’ll certainly be keeping an eye
out for further developments in this regard.

Zycube CIS

Last week Zycube made a presentation
which revealed some very interesting details about their CIS
technology. In their product roadmap (shown below) they indicate
that image sensor + DSP is the next product on their roadmap.

A question came up about side wall
insulation and back side interconnect after Zycube indicated that
the device should not see more than 200 C due to color filter
limitations. Zycube responded that the insulation was indeed SiO2
formed by a special low temp TEOS deposition process and that the
density of this oxide was good enough for this application. They
also showed pictures of their 2 µm

(yes – two micron) InAu bump
technology for bonding.

They noted that future generation
stacked products would need < 30 µm wafer thickness, <
5 µm micro bump pitch and would have to allow for more than
20K chips/hr placement with less than 0.2um alignment error (a tall
order for current pick and place tools) .

Micron joins the CIS TSV
gang

There was also buzz about Microns
recent announcement that the company will place the CMOS imaging
division in a separate company, Aptina. 700 Micron employees are
involved - based mostly in San Jose, Calif. Aptina calls their
wafer level TSV technology “WLC” for wafer level
camera. As is usual with Micron not much has been released
concerning the technology, but from pictures its basically their
response to the recent announcements of their competitors.

New Cu-Cu bonding technology
on the Horizon ??

Maybe the most important
breakthrough was hinted at by Lea Di Cioccio of CEA
Leti. As she ended her presentation on available Leti
technologies she mentioned that they have developed a “…new
room temperature and pressure Cu-Cu bonding technology”. The
bond strength of blanket Cu films is reported to be 2.8 J/m sq
without annealing. After bonding a separate anneal step ( 150
– 400 C) is used to strengthen the interface. When pressed
during the Q&A session she indicated that further details would
be given at this years IITC (mid June).

The importance of this observation
is throughput, which may be the last battle in 3D
commercialization. It is generally accepted that Cu- Cu or Cu-Sn
eutectic bonding is favored because it forms both the mechanical
and electrical bond at the same time. It is also generally accepted
that such vias first technologies are significantly easier to
manufacture than the alternative vias last technologies. The one
issue that remains is throughput - where generic Cu-Cu bonding
technology of highly polished Cu surfaces takes ca. 30 minutes
under slight pressure at 350 to 400 C in an expensive bonding tool.
If the technology described by Ms Di Cioccio is manufacturable this
would be a major leap forward.

The weather around Scottsdale was
just great. The group shot below was taken after a leisurely night
of drinking after the 3D panel session. Can you pick out any of
your friends, suppliers or customers in the photo ??

More from IMAPS in the next blog.
For all the latest on 3D IC Integration stay linked to
………….Perspectives From the Leading Edge