Best of the Rest at 3D ASIP
In this last blog covering 3D ASAIP
2008 I will try to cover some of the more interesting information
presented at the conference.
Jan Vardaman –
TechSearch
Vardaman is sticking by her 2007
very conservative predictions for 3D IC adoption with DRAM / SRAM .
She still sees DRAM not happening till post 2010 and NAND not
happening till later than that.
Jeff Perkins –
Yole
Yole, on the other hand, is
standing by their aggressive adoption curve for 3DIC in general and
especially for memory. Yole indicated that 0.3% of the 155B
packaged devices produced in 2007 were done with TSV. (That’s
~ 0.5B devices when you do the math). They are predicting 100K DRAM
wafers in 2009 and 14% of ALL wafers processed and 9% of non memory
wafers by 2015( see figs below). As I told them “…for the
sake of the technology I hope you are correct….but all my years
in the industry tells me that your not”. Time will tell who
is correct here. Note that these numbers have actually changed
considerably since their 3D ASIP presentation one year ago where
they predicted 20% of the DRAM market and 30% of the flash market
would be using 3D IC in 2012 [ see
PFTLE “3D
discussions in the valley continue” Nov 4th
2007]
Also of interest was the comment
that there were now (8) 300 mm 3D IC lines operating worldwide.
Tegal (Alcatel)
Tegal indicated that PECVD SiO2
deposition could be done at < 150 C with a deposition rate of
500 nm / min. They also indicated that coverage for AR > 3 was
“difficult”
Brewer
Customers are asking for the
temp bonding process (during wafer thinning) cost to be <
$10 / wafer and looking for 25 wafers/hr throughput.
Nexx – talked
directly to Dick Post Chairman of Nexx who indicates that the
purpose of their license of the Alchimer technology is to qualify
current Alchimer technology on their Nexx deposition tools. Post
envisions a possible Alchimer “module” available from
Nexx. Instillation at customers would be a joint Nexx / Alchimer
endeavor.
Tezzaron
More from Bob Patti on Cu vias:
Aside from size and shape affecting reliability, Bob also indicated
that any voids in the Cu vias (due to seams from non bottom up
filling) tended to migrate under bias to the signal traces and
cause opens. Cu expansion (due to CTE mismatch) was also seen
affecting strained silicon.
Exclusion zone - they have
found that for analog devices the vias need to be ca. 10 diameters
away from the circuit so as not to have electrical impact. For W
they found this “keep away zone “ was only 0.4 –
0.5 um.
Motoyoshi –
Zycube
An interesting comment was that the
sidewall insulation deposition temperature was limited by the lens
stability temperature which he reported to be 180 C . Since
these CIS device are being operated at 3.3V the density and thus
breakdown voltage obtained by CVD deposition of SiO2 at these temps
was considered OK.
Truzi –
Alchimer
Described their full “Aquivia
“ process which is to be released in 2009. It will include an
all wet process for deposition of conformal insulation, Ni
barrier and copper seed layers.
Claudio shared the first data on
their electrografted dielectric which they are indicating
they will commercialize in 3Q 2009 . Although not identifying the
material, he reported a K of 3.0 – 3.6, a breakdown voltage
of 4-6 MV/cm and stability for > 2 hrs at 400 C. Those
would be very interesting properties so I can’t wait for
further information.
For all the latest information in 3D
IC Integration stay linked to Perspectives From the Leading
Edge…………………..
