Highlights of 3D ASIP

Without question the title of the
RTI sponsored 3D Integration conference “3D
Architectures for Semiconductor Integration
and Packaging” is a mouthful and I therefore propose
the following acronym 3D ASIP.

The 5^th annual 3D ASIP
Conference proved once again to contain the most complete technical
and commercial coverage in the area of 3D IC of all the available
meetings. If your wanting to know where the technology stands
and/or commercialization stands, this is the meeting to attend.

In the last PFTLE blog I
covered the main take home messages which I felt were (1) a plea
for further standardization and (2) the indication from both IBM
and Tezzaron that there were issues appearing with copper TSV in
some shapes and sizes. In this blog I will try to summarize the key
points of the Keynote presentations by IBM, Intel, Micron, and ASE
and see if there were any commonality in them.

Mike Shapiro – IBM
Chief Technologist 3D Development

Mike gave us some reminders of why
we were interested in 3D integration. A lot of them were issues we
have covered before. We covered his warnings about TSV reliability
and his industry plea for common TSV integration approaches in the
last blog. Another interesting concept was “modularity”
or reuse of technology layers to develop new products. A 3D centric
way to lower cost and speed time to market (see fig below)

Shekhar Borkar – Intel
Fellow

Shekhar approached the “why 3D
?” question from an Intel perspective. The fig shown below
indicates that both frequency and chip size are being limited by
power.

He also spoke to the limitations of
system in package (SIP) in terms of limited pins and higher power
requirements due to signal lengths (see below)

During an extended look at the
memory on processor 3D IC stack he pointed out that DRAM is best
used at < 85 °C and that in the preferred DRAM / SRAM
configuration (memory on the bottom), power and I/O must be routed
through the memory die. Such a 3D memory architecture results in a
10X reduction in power to drive the I/O as shown below.

One issue that did come up during
questioning was that the now famous 300 mm 80 core processor wafer
with stacked SRAM memory was designed by hand since no software was
available. Another indication that software availability may be
gating technology adoption.

Gurtej Sandhu – Micron
Director Advanced Technology

Gurtej was also a strong proponent
for common TSV integration approaches. His slide on cost
sensitivity vs performance requirements for various applications
(below) is right on the money and is why PFTLE has indicated that
DRAM will proceed NAND on the 3D integration timeline [ see PFTLE
“3D IC questions and answers with the EMC-3D
Consortium”, Oct 4^th 2008].

In fact Micron points to a current
5X cost difference for TSV vs today’s stacking technologies
as they apply to NAND (shown below)

Of great interest were Gurtej
comments that “Via First” BEOL integration scheme had
been selected by Micron as the best approach for DRAM memory
applications and that for the best electrical performance scaling,
Cu was selected as the via fill material.

Though not as explicit as the
comments from IBM and Tezzaron, Gurtej also pointed out that
thermo-mechanical stresses needed to be determined vs TSV diameter,
AR and pitch. In addition Micron has been one of the only companies
pointing out that via capacitance varies linearly with die
thickness and inversely with via pitch. For fixed via size, tighter
pitches can be achieved with thicker insulator dielectrics, but we
all know that deposited SiO2 layers have a very limited thickness
range [ ~ 1-1.5 um] before they crack.

Another interesting slide (shown
below) was of the most interest because of the changes made to it
since it was last shown by Kyle Kirby [ see PFTLE “ Road
Trip Revelations”, May 18^th 2008 ]. The
columns previously labeled tomorrow and future are now labeled near
future and far future. That now keeps the TSV AR in the <
5 range for the foreseeable future (a position that PFTLE has been
supporting for some time now) and PFTLE is now fully on board with
these revised Micron timeline projections.

Lastly, Gurtej showed a summary
slide (shown below) which identifies the “majority approach” (in
green) for the various unit operations necessary for 3D IC. I would
tend to agree with all of these except maybe the bonding
technology. I have not seen that a majority of practitioners have
moved to Cu/Sn eutectic YET !

Ho-Ming Tong - Chief R&D
officer ASE

TSVs show up on the ASE packaging
roadmap at the 32 nm node. Ho-Ming pointed out that ASE
demonstrated vias last (backside TSV) at the 65 node on the
structure shown below.

The issue of who will do what in the
infrastructure was addressed very nicely by the ASE slide shown
below where the “vias last” would be a typical CIS
product . PFTLE agrees with ASE that the thinning and bonding could
be done by either the FAB or the OSAT.

Another very nice slide shown below
indicates ASE thoughts on equipment readiness. This is the first
time I have seen such data from a user (vs suppliers). Looks like
nearly everything is about ready except TEST !

Ho-Ming concluded with the comments
that an ASE 200 mm line has been in place for 3D IC for 2 ½
years. They would like to see vias last commercialized first [ as
well it is because of CIS ]and that two 3D IC products are
scheduled to go into production at ASE in 2009.

Check back next week and I’ll
be covering some of the key points of the remaining
presentations…..

Coming soon…..

……………Highlights from the
IMAPS conference……

……………What are
technologists saying at the MRS 3D sessions ?……

For all the latest in 3D IC
information stay linked to Perspectives From the Leading
Edge…………………