ASET drives 3D Integration workshop in Tokyo

I think it was Charles Lassen (who
retired from Prismark several years ago and is now sailing the
Mediterranean with wife Susan) who once showed me a slide which
proved that technology does not become “commercial”
until after publications in the area peak and actually begin to
decline. The data was irrefutable and held up across a wide variety
of microelectronic technologies. With that as a given, I can tell
you that 3D Integration “…is not there yet” The May
– June time period saw a 3 day focused workshop in Tokyo,
several full day sessions at the IEEE / EIA sponsored Electronic
Component Technology Conference (ECTC) and a focused session at the
IEEE IITC. Over the next few weeks as we head towards Semicon West,
I will be highlighting some of the more important / interesting
information that was shared at those venues.

The second week of May saw the 3D
– SIC workshop in Tokyo. It was set up by the ASET
2 (Association of Super-Advanced Electronics Technologies)
group [ see Perspectives from the Leading Edge “More TSV capacity
comes on line” – 12/05/2007 ]. It was Co-sponsored by a
long list including the Electrochemical Soc (Japan), IEEE Electron
Device Society (Japan), SEMI Japan and most importantly was
financially supported by METI and NEDO.

After the requisite introductory
presentations the focus of the individual sessions was around
design, reliability and system issues, which are the known focus
areas of ASET 2.

Kiwook Lee, from
Amkor, detailed the work they are doing in RTP,
their involvement in the IMEC consortium and the Korean 3D
consortium where they are working with Samsung and Hynix. They
indicated that they are currently focused on:

• carrier technology
• wafer thinning technology
• BSM (back side metal – i.e. redistribution)
• chip to wafer bonding technology

They feel that they have developed
manufacturing capability for thinning and bonding both Cu and W
TSV. They showed their carrier wafer technology for thinning and
how various analytical techniques were used to confirm the lack of
Cu smearing / migration in the Si areas surrounding the Cu TSV and
/ or W via cracking. Cu fusion bonding was compared to Cu/Sn
eutectic and Sn solder bonding.

In terms of carriers, they showed
the following chart comparing glass to Silicon.

The slide below depicts the
relationship between thinning and process cost / difficulty. As I
obsessed on in the last blog [ June 8^th Perspectives
from the Leading Edge - “If It’s Thursday it must be
San Jose” ] , low aspect ratio is a good thing for TSV
drilling and filling, so thinner die means lower process difficulty
and process cost.

Lastly, a nice little chart showing
what I consider is another key to 3D – metal- metal bonding
throughput [ see May 28^th Perspectives From the Leading
Edge – “Road Trip Continued” ]. Here Amkor shows
Cu/Sn being a lower temp and lower time process – which it
is. As we have noted before, 30+ minutes in the bonding tool
requires multiple bonding heads in the aligner bonder tool and is
therefore a COO issue.

Shekhar Borkar from the
Microprocessor Technology Labs at Intel gave a
system level perspective on the 80 core multiprocessor that Intel
first revealed was being prototyped with TSV back in 2006. Since
DRAM technology was not available, they used SRAM to demonstrate
the concept. This initial TSV pitchof 190 um is described as
“modest” but adequate to deliver “…coarse level
integration of memory and power delivery to the CPU”.

In one of the introductory
presentations Eric Beyne of IMEC focused in on the
requirements of cost 3D integration. I’m especially
supportive of his conclusions about how and when to do TSV
processing. (paraphrasing) “…For current VLSI technology
the limiting factor for circuit density is often the routing
capacity of the BEOL interconnect layers…Having large and high
density TSV through the BEOL interconnect layers , blocks the
routing channels and could, in fact, end up requiring more
interconnect layers on the chip…..In addition the BEOL layers of
advanced IC processes consist of complex stacks of oxides,
nitrides, carbides and low K materials as well as dummy metal (Cu)
structures required for proper CMP. Etching TSV through BEOL stacks
is extremely difficult and may compromise BEOL
integrity…”.

(paraphrasing again)
..”…therefore TSV connections should be made first and
buried below the BEOL layers (i.e. foundry vias first) or done post
processing, (vias last) after thinning, from the backside (as is
done for current CMOS Image sensor devices).

ERIC –
I could not agree more !!

next blog we will begin to look at
some of the technology shown at the 2008 ECTC Conference.

For all the latest on 3D Integration
stay linked to Perspectives From the Leading
Edge……………………………….