IITC on the 3D Integration Bandwagon

Back in February I welcomed the IEEE
IITC Conference aboard the 3D Integration bandwagon [
Perspectives From the Leading Edge – 2/26/2008
“IMEC
Setting up Shop in Hsinchu”]. After being a bastion of
“Low K integration” for the last decade they certainly
need to move on. We all recall that the ITRS roadmaps told is in
1998 that the on chip Keff would be 1.6 by 2007. Probably the
lesson to be learned here is not to allow your roadmap committees
to be overloaded with “pseudo technical” marketing
folks from the materials/equipment companies – kind of like
letting realtors create your town zoning ordinances ! From a
scientific standpoint their bravado never made any technical sense
and in the end all things do need to make sense.

Anyway a technical shift at IITC is
now occurring as evidenced by the recent 3D integration session at
their June meeting.

The most anticipated paper of the
session had to be from TSMC. Since their recent 3D
integration announcement [ see Perspectives From the Leading
Edge 5/02/2008 “The
Foundries they are a comin’ – TSMC makes their play for
a bigger portion of the pie”] the industry has been
eagerly awaiting information on their process / processes. The
presence of this paper indeed was a coup for the IITC conference.
The presentation by HJ Tu, while not divulging their ultimate
preferred process sequence did show enough real data to indicate
that they are serious about what they call “3DIC”. They
showed both Cu and W vias with AR of 8:1 and 15:1 (Their logic here
is that they do not yet know how thin they can go without impacting
the electricals of the die). They claim routine alignment accuracy
of < 1 um and indicate that they are looking at lower temp
bonding processes so they can minimize alignment issues due to CTE.
Data for low resistance Cu-Cu interfaces are shown and indications
that their process is at ca. 80% yield (based on daisy chain test
structures). We all eagerly await further process data from
TSMC.

Scott Pozder and the
Freescale group in Austin reported on their work
with Datacon, Cookson and EVG to examine die to wafer Cu/Sn
eutectic bonding with no flow underfill. The copper pads on the
acceptor wafer were ca. 50 um and the pads on the die were ca 20 to
40 um to allow for 15 um miss alignment and therefore faster chip
placement. After Datacon F2F KGD placement, the die were bonded /
underfill was cured with a bond force of 2-4 kN at 270 C for 30
min. Such parts passed significant rel testing. Mechanical
robustness was tested by thinning the bonded die fro m280 to 50 um
without any die disruption.

In Perspectives From the Leading
Edge 3/23/2008 “3D
Practitioners Assemble at Ft McDowell” I indicated that
Leti’s Lea Di Cioccio had teased us with an
indication that “…room temperature and pressure Cu-Cu
bonding technology” was in development. At IITC they gave
further data in Pierric Gueguen’s paper and Patrick
Leduc’s paper at the 2008 IEEE Int Symp VLSI.

Also of interest is their
examination of parasitic coupling between TSV and CMOS transistors
(65 nm node). TCAD and SPICE simulations show that digital
applications should not be impacted by TSV at distances > 5 um
whereas analog applications, especially at RF appear more
sensitive.

Direct copper bonding at room
temperature and atmospheric pressure were investigated for
patterned Cu wafers. After anneal at 150 C the Cu-Cu bond energy
was 1.2 J/msq (see fig below). The thinning of the bonded pairs
down to 10 =m without delamination indicated a high mechanical
strength of the bond. Electrical testing, TEM and EELS analyses
confirmed the absence of oxide at the bonding interface. Although
full structures have yet to be built, these Leti researchers
conclude that RT Cu direct bonding is a possible approach for D2W
or W2W Cu-Cu bonding below 200 °C.

Also of interest from
IMEC was the report of Riet Labie on
electromigration resistance of Cu/Sn eutectic bonds.

Electromigration is a well-known
cause for long-term reliability problems in solder bonded
structures. Unlike standard solder flip-chip structures, in Cu/Sn
eutectic bonding, all solder material (read Sn) is transformed into
intermetallic during the bonding process. These intermetallic
joints are shown to be highly resistant to electrical loads. For
Cu-Sn, a phase transformation is observed which modifies the
initial 2-phase state (with both Cu3Sn and Cu6Sn5 layers) into the
thermodynamically favorable high Cu-containing single intermetallic
phase.

After 1000h, no failures or
degradation mechanisms are observed for testing conditions (150 C
and 0.63mA/sq um which are 10x the current density compared to
electromigration triggering values for standard solder flip-chip
applications (0.05mA/_m2). Thus, although standard solder Cu-Sn
interconnections with remaining Sn after the bonding process are
strongly susceptible to electromigration degradation, the fully
transformed intermetallic system is extremely stable.

For the latest updates on 3D IC
integration stay linked to Perspectives from the Leading Edge
………………………………….