.......If it's Thursday it must be San Jose

A few weeks back, while on the Suss
/ STS / NeXX road tour across the US, I felt like I was on one of
those tours of Europe that were popular back in the 60’s. You
know…the ones where you visit one country per day and after a
while the only way you know what day it is, is by the country you
are in. By the time Thursday in San Jose rolled around I felt like
I was repeating myself….cause I was, only in different cities. As
the slides continue to flip you find yourself thinking
…”..didn’t I just cover that one ??”

In San Jose it was great seeing Ed
Korczynski in the audience. Ed is Sr technical editor over at Solid
State Technology and his blog, over there, is one of my favorites.
I like when things are logical….Ed seems to be the same way.

Last week I said I’d make some
comments on the road tour presentation that Bob Lanzone, of Amkor,
made in RTP earlier in the week. Bob, who gave no handout, is
having trouble getting a lot of that material cleared for this
blog, so while I’m waiting, I’ll make some comments on
the OSATS in general. Two years ago, to the man, Amkor, ASE and
STATSChipPac , were espousing the position that THEY would be doing
the via fabrication in future 3D integration manufacturing
scenarios. More evidence of that position comes from the EMC-3D
consortium (started ca 2.5 years ago). If you go to their web page
you’ll see that they are focused on a vias last approach
which was in vogue at the time.

If you ever worked with me , or, are
a reader of this blog you know that one of Garrou’s rules is
“ …do not be misled by the literature. Early on in a
technology development, engineers do processing the easiest way
they can to prove out the device concept. They use the tools that
they have on hand and the unit operations that are available…they
are not working on manufacturability or cost reduction” So
while the overwhelming # of 3D papers are still written about vias
last, logic and a basic understanding of the microelectronics
business infrastructure, have told me for quite a while now that
vias first at the foundry or the IDM make the most sense. OSATS
will be relegated to “…thinning , bonding, backside
redistribution and packaging” which is really what they are
good at. The labor is cleanly divided this way and everything makes
sense. There have been a lot of “nay sayers” the past
few years, but the recent announcement by TSMC, declaring
themselves a player at the 3D integration table, has slowed that
down quite a bit.

Anyway, the OSATS in general, and
Amkor in particular ( not only Lanzone but also CJ Berry and Lee
Smith), now seem to be aligned with this concept…. cause it makes
technological and business sense.

Getting back to Lanzone’s
presentation, Bob indicated that Amkor is seeing 3D designs where
memory is being de-embedded ( or is it disembedded ??) from devices
and F2F bonded on top of it. Are we seeing acceptance of the 3D
concept that optimizing processes individually and then mating them
is in the long run a better way to go ?? Recall I mentioned last
week that Tezzaron is also seeing acceptance of such “split
die technology”. If the basic concepts of 3D are
valid….this also makes sense and thus we will see this as a
growing trend.

BEWARE OF THE ASPECT RATIO (AR)

I’ll finish off the road tour
comments with a rant on one of my favorite 3D “pet
peeves” ASPECT RATIO. I first brought this up in public at
the Semitool Peaks for Packaging conference last fall. It involves
another Garrou rule for field engineers and technical sales folks
“ always ask the customer what he needs and then make sure
you challenge him as to why ! “

When the equipment and materials
vendors meet with potential 3D customers and ask what they will
require, the customers are “requesting the moon”. You
know what I mean here…if you’re a dielectric supplier your
customers ask for a Dk < 1, a chameleon CTE and a cure
temperature of 25 °C.

In this case it is important to know
what aspect ratios will be required for various diameter vias both
in terms of making the holes and filling them. Most COO models show
that via formation and via filling are the major cost obstacles for
3D ( but this obviously depends on size, pitch and AR). What
I’m seeing is the tool vendors and materials suppliers
working hard on aspect ratios of 10:1 and 20:1 . When I ask them
exactly what applications these AR are for, they cannot
answer….but they know the customers have asked for such
dimensions.

To agree with the position that I
will take (below) the only leap of faith that you need to make is
that as 3D technology evolves and all applications see via and
pitch shrinkage , along with this will come a decrease in layer
thickness. The tests that have been done so far show no deleterious
effects from backside thinning down to sub 5 um Si, so electrical
performance will not be the limiting factor, it will be
manufacturability.

If we look at image sensors the
current vias are 50+ um and the layer thicknesses are 100 to 150 um
. Hummmm….no 20:1 aspect ratios here. Looking at CIS roadmaps
they are projecting smaller vias and thinner layers and at no point
do I see an aspect ratio > 5:1

Looking at memory stacks we see the
same thing. Samsung is showing 50 um thick Si and vias of 25 - 35
um. The roadmap shows shrinkage to 10-15 um vias on 20 um layers
comes next. Even if they left the thickness at 50 um this would
still be 5:1 in the worst case.

Same for memory on logic …check
out the Intel prototypes for DRAM on processor and you will see 4-5
um vias in a bonded 10 um Si memory chip. To think they will shrink
via size to 1-2 um and not further thin the wafer simply makes no
sense.

So, high AR may be needed for MEMS
or some other applications, but for 3D I see nothing mainstream
required above 5:1. If these applications are out there please tell
me what they are !

So I conclude, lets put the effort
where it is warranted ….and that’s not in making 10:1 -
20:1 AR vias but rather in optimizing thinning technology (whether
on a handle or on the 3D stack) alignment technology ( can we
really get sub micron alignment from tools we can afford to buy? )
and bonding technology ( lets get the metal metal bonding
throughput up with technology concepts like the Ziptronix DBI
mentioned last week).

I’m going out on a limb here,
but I really think that in the end chip to wafer alignment and
bonding will be the COO issue not technology for 20:1 AR. ….but
as Dennis Miller would say….”..that’s just my
opinion…I could be wrong !”

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to…..Perspectives From the Leading Edge…….