3D Road Tour contd

Picking up where we left off last
blog with 3D Integration news from the recent Suss/STS/NeXX road
tour I’d like to point out some highlights of the
presentations of the two longest lived 3D start-ups Ziptronix and
Tezzaron.

Tezzaron

We have discussed the Tezzaron 3D
memory technology previously. [ Perspectives From the Leading
Edge – “more
3D IC Integration in the AZ desert” April 2008 ] Recall
Bob Patti, who already has Chartered fabricating his vias first 3D
memory structures, has indicated that (2) other fabs will soon be
announcing their adoption of the Tezzaron technology.
Well…no announcements yet, but we did get some valuable new
information. The figure below shows Bobs attempt at charting the
number of vias required to access different levels of a chip.
Standard memory, for instance, requires only 10 TSV per sq mm to
connect chip to chip through the normal rows of I/O pads whereas
1000 TSV per sq mm are needed to access at the block level. Bob
claims the Tezzaron technology which can create TSV on a sub 2 um
pitch can actually be used to connect on the function and gate
level [but not today ].

We also got some additional insight
into the technique of KGD to wafer bonding for Tezzaron. The figure
below shows how a physical template is overlayed onto the wafer
prior to KGD transfer. This template allows for a rapid alignment
of all the die before the bonding process.

Bob claims he is actually seeing a
trend where designers are de imbedding memory in order to take
advantage of 3D integration. He has coined the term “split
die technology” for this phenomenon.

• Split Die is an alternative approach to embedding memory such
  as DRAM, Flash or even large SRAM.
• Memory is directly bonded using Tezzaron’s FaStack die to
  wafer, face to face attachment.
• Split Die provides performance as if the memory were made on
  the original host device but with the density of external memory
  devices.
• Split Die Memory are manufactured in memory centric processes
  offering improved density at lower cost per bit.
• Typical attachment cost is < 0.01 cents per connection

Ziptronix

Ziptronix spun out of Research
Triangle Institute (RTI) in 2000, so they have been at this for
awhile. They have been ahead of their time in the 3D integration
arena. They have a significant patent portfolio in wafer and die
bonding technology, especially low temperature oxide to oxide
bonding which they call Zybond™.

Normally, this would not excite me
since you probably have picked up by now reading this blog that
when it comes to 3D integration, I am a fan of two things (1) vias
first – i.e. let the fabs do the TSV and (2) metal - metal
bonding – i.e. lets get the mechanical and electrical
connections done at the same time. So, you might ask, how does
Ziptronix oxide fusion bonding technology fit these criteria??
Well, within the past year or two Paul Enquist, CTO, has introduced
what they call “DBI™” (direct bond interconnect)
the premise of which is CMP’ing oxide and metal interconnect
plugs coplanar and using the exposed oxide surface,
“treated” by one of the many Ziptronix patented surface
treatments, to bond the dies or wafers in a standard bonder/aligner
tool. The key here is that normal copper-copper fusion bonding in
such tools takes 30 – 45 minutes per wafer pair at 350
– 400 C, under pressure, whereas the Ziptronix oxide bonding
takes place in 1-2 minutes under ambient conditions. The Ziptronix
wafers are then removed from the aligner bonder tool and loaded
into an standard clean room oven for the metal-metal bonding
process. Since the coplanar oxide layers are fused together they
hold the interface under pressure when the metallic interconnect
expands at elevated temperature and , at temperature, forms a
monolithic metallic interface. This results in greatly enhanced
throughput and thus lower COO (cost of ownership) for the bonding
operation.

The Ziptronix process flow is shown
in the figure below. I have heard from some practitioners that they
are wary about the identity of the mysterious DBI metal. Ziptronix
is glad to share that info with anyone under secrecy. I now know
it’s identity, which I cannot share with you here, but can
tell you that Enquist is correct when he indicates that while it is
not commonly used by front end IC fabs today, it is used by many
assembly and packaging houses and would not be an issue installing
into any 3D integration line that I know of.

Paul showed data indicating that
test structures containing 1MM bonded pairs on 10 um pitch showed
interface resistances < 0.5 ohm/um sq and passed 1000 thermal
cycles (-65 to +175 C) and HAST testing.

Lastly Ziptronix indicates that
image sensor fabricators are looking at their Zybond technology to
do oxide oxide fusion bonding of sensor device wafers to handle
wafers. They subsequently grind and polish off the sensor substrate
to allow enhanced sensitivity and resolution by backside
illumination of the sensors.

Comparisons

When we compare the processes being
used by these two start ups we see that both processes prefer vias
first technology and both use metal-metal bonding to achieve wafer
and/or die stacking. Another commonality is that both suggest the
thinning be done after stacking in order to avoid the whole carrier
wafer – temporary adhesive attach and de attach process. They
are not limited by this sequence, but rather are highly compatible
with avoiding it, to again result in an overall process with lower
COO.

If your looking for the highest
performance memory in the smallest form factor around take a look
at what Tezzaron is offering. If your looking for a flexible low
COO 3D itegration bonding process to install, that is CMOS
compatable take another look at Ziptronix.

In the next blog we will finish up our discussions on the road
tour with a look at some Amkor announcements from Bob Lanzone and a
few other interesting tid bits.

For the latest info on 3D IC
Integration stay linked to Perspectives From the Leading
Edge………………..