Opening the Kimono, Ziptronix gives details on DBI Process

I hear from my
Japanese friends that the phrase “open kimono” is NOT
of Japanese origin but rather is an American phrase using a
Japanese word. Best I can tell it stems from Silicon Valley during
the 1980s Japanese acquisitions of US companies. At a certain point
in the negotiations the US companies were ready to reveal the inner
workings of the company to the perspective buyer / partner. At that
point the Kimono was opened to show the buyer the real goods, so to
speak.

I recently had a
chance to interview the principals at Ziptronix and the content of
that interview was distilled down into the article in the Oct
Semiconductor International print edition. Their decision was to
begin to “open the kimono “ on their DBI® process
and give Semi International an exclusive on exactly how it works.
They will be expanding on this even further in their presentation
at the RTI 3D conference in Burlingame in November and the MRS fall
meeting in December. You may have come across other interviews of
Ziptronix recently, but notice no process details on DBI were
divulged there. I thought I’d use this weeks PFTLE blog to
expand upon the print interview and give some more insight into
what they claim they can do, and why it’s
important.

Background

Ziptronix spun
out of the “High Speed Materials and Devices
Laboratory” in Research Triangle Institute (RTI) around the
turn of the century. The key technologists in forming the new
company were QY Tong and Paul Enquist. Dr. Tong has since passed
away, leaving commercialization of the Ziptronix technology in the
hands of Enquist and the management team that has been put in
place.

You may not
recall, but Tong along with his research collaborator Ulrich Gosele
( Max Plank Institute and Duke University ) wrote the first wafer
bonding book “Semiconductor Wafer Bonding: Science and
Technology” a decade ago. To many this is still the key
treatise on the subject (see below). Back then, wafer bonding
technology was not focused on 3D integration, but rather was a key
technology for SOI and for the bonding of dissimilar non Si
semiconductors.

What have
they done ?

While at RTI and
after the spin out, Ziptronix has done extensive R&D on low
temperature oxide bonding technology. It was already well known
that extremely flat and smooth SiO2 surfaces (RMS roughness < 1
NM) in an extremely clean environment would bond. The issue was how
to achieve bond strengths that would allow subsequent handling and
processing yet not require annealing at ~ 1000 °C. ( see
above)

Ziptronix’s
extensive patent portfolio revolves around their ZiBond ™
(CMOS compatible Direct oxide bonding). Their IP and published
papers reveal that bonded silicon wafers (with at least 1 wafer
coated with oxide) after various surface activating and terminating
treatments, show significantly higher bonding energy than standard
cleaned wafers after low-temperature annealing. For instance the
bonding energy using some of the Ziptronix treatments reaches over
2000 mJ/m² after annealing at ~ 100 °C ( the
fracture energy of bulk Si is 2500 mJ/m² ). In one
embodiment of their ZiBond™ IP (shown in the DBI process flow
below) the oxide surface is treated with plasma followed by a
aqueous ammonium hydroxide treatment.

The DBI®
(Direct Bond Interconnect) process flow is shown in the figure
below. Ziptronix has now revealed that in one preferred embodiment
the DBI metal is Ni, which can be CMP polished at the same time as
the oxide surface without getting any “cupping” that
can happen with some metals like Cu. This is obviously a key to the
DBI process, i.e. achieving the necessary extremely flat surface so
that metal-metal contact occurs when the die (or wafers) are
aligned and bonded. This process can easily be performed by any
OSATS or IDMs who are currently doing bumping or wafer level
packaging. Actually, for many of the OSATS, installing and
qualifying a CMP process would be more of an issue than the oxide
treatment or the DBI metal plating.

Subsequent oxide
bonding typically takes place on a pick-and-place tool (D2W) with
bonding time, as you would expect, dependent on required placement
accuracy . W2W bonding on a standard wafer aligner / bonder is also
possible. Wafers are subsequently stacked in a conventional
standard clean room oven and exposed to 300 °C. Since the
exposed oxide layers are bonded together, they hold the interface
under pressure when the metallic interconnect expands at elevated
temperature and forms a monolithic metallic bond. This results in
greatly enhanced throughput and reportedly lower COO for the
bonding operation.

Why is
this Important

If we stand back
and look at 3D integration developments we see an industry
struggling with throughput on the direct copper- copper bonding
process. Current processing which currently requires bonding at 350
- 400°C for 30+ minutes has required commercial aligner /
bonder tools for W2W bonding to have multiple bonding heads in
order to achieve 3-4 wafers per hour throughput which dramatically
increases tool cost and thus negatively impacts COO.

In terms of D2W,
we have recently discussed data shown by EVG [ see PFTLE
“3D
Integration stays HOT at Semicon West” Aug 13^th 2008] showing that the best
throughput is achieved by oxide bonding, oxide bonding has 35%
better placement accuracy today and has the best potential for
future accuracy improvement and that oxide bonding provides a 10X
faster process !

From the pie
chart and answers to direct questions in the last blog [see PFTLE
“3D
IC Questions and Answers with the EMC-3D
Consortium” Oct 5^th
2008] we saw that bonding has a significant impact on overall
COO.

If this
information is all accurate, this Ziptronix process surely deserves
a serious look !

While they are
not free to announce who, Ziptronix indicates that they are seeing
increased interest from IDMs, foundries who have recently announced
that they will be supplying TSV’s as part of their fab
service and OSATS who are in the process of developing thinning and
bonding services.

In keeping with
the application timing previously laid out by PFTLE, Ziptronix sees
their process becoming commercial first in CMOS image sensors as
they move to backside illumination which requires low temp and low
COO oxide bonding technology to make it economically viable. [ see
PFTLE “Backside
Illumination (BSI) Architecture next for next Generation CMOS Image
Sensors”, Aug 3^rd,
2008]

Another short term opportunity that I have not seen discussed
yet is to use DBI® technology for high density F2F
(face-to-face) CoC (chip-on-chip) bonding where no TSV are
required. At the end of 2005 Sony implemented CoC,
bonding DRAM directly to logic for the
playstation. Infineon / IZM Munich have also
described similar technology with their acronym
“SOLID”. [ see PFTLE
“3D IC Integration: Evolution or revolution” 3/16/2008]
and [“Chip-on-Chip Offers
Higher Memory Capacity, Speed”
Nikkei Electronics Asia, February 2007]. This is currently being done with micro bump
bonding, but perhaps could be done at higher density or lower COO
by using DBI.

PFTLE will certainly be keeping an eye on Ziptronix how this their
DBI technology develops.

For all the
latest on 3D IC integration stay linked to
PFTLE…