Fisk, Buckner and Pasta on the North End

Having spent a decade of my life
there, I came to know and love Boston as a great East Coast city. I
define my Boston decade by two of the great moments in the history
of “Red Sox Nation”, since my arrival coincided with
Carlton Fisk willing his HR fair in the 1975 World Series and I
left town shortly after Billy Buckner let the ground ball scoot
through his legs in the 1986 World Series. Aside from baseball, I
truly loved the North End where you could discover a new, Italian
restaurant every weekend, if you so chose, and believe me I did. So
anytime I can find an excuse to go back to Boston, I usually do so,
in order to indulge myself with great baseball and fine pasta.

In the last few years I have taken
advantage of the MRS meetings held early every December in downtown
Boston to enjoy the town and pick up some very important 3D
technical information.

In this weeks blog I’ll cover
the papers on 3D bonding presented a few weeks ago at MRS and next
week I’ll update you on some of the other interesting 3D
topics that were presented there.

Ziptronix

In October PFTLE gave you
advanced notice on details of the Ziptronix DBI technology [
PFTLE, “Opening
the Kimono, Ziptronix gives details about the DBI
process” 10/14/2008] . At this MRS meeting they continued
to share details about their low temperature direct bonding
technologies. Recall, in this technology two co-planar surfaces of
metal/insulator are direct bonded at room temperature. Bonding
initially takes place on the activated insulator (i.e.
SiO₂) surfaces. Subsequent heating of the bonded
structures in a standard clean room oven then forms a monolithic,
low resistance metal-metal interface.

Ziptronix has previously indicated
that the DBI metal can be Ni (required thermal treatment of 300
°C), which was chosen because its hardness allows an easy CMP
process to generate the required coplanar surface. In this
presentation Enquist further divulges that DBI can also be
practiced with Cu, W and Au, (amongst other metals - see USP
6,962,835 ) and promises data will be available soon on 3 to 1.5 um
pitch structures using these alternate DBI metal choices. We
will be keeping an eye on any future Ziptronix announcements.

CEA Leti

Low temperature direct bonding was
also the theme of the presentation by Lea DiCioccio of CEA Leti. We
have been keeping an eye on their Cu-Cu bonding work [ see
PFTLE “IITC
on the 3D IC Bandwagon”, 07/07/2008]. In this
presentation DiCioccio describes direct Cu-Cu hydrophilic bonding
where the Cu surface is “treated” to make it
hydrophilic by a technique not yet described and then CMP’ed to 0.4
nm rms . Initial Cu-Cu bond strengths were found to be 3+
J/m² but dropped after annealing at > 100 °C to
ca. 1.5 J/m² (see fig below) They determined that this
was due to delamination at the TiN (barrier layer) /
SiO₂ interface which they eliminated by switching to TaN
barrier layer.

In order to test the electrical
resistivity of the bonded Cu interfaces, Kelvin structures created
in patterned in a SiO₂ oxidized wafers were bonded face
to face in an alignment tool (see Figs below). After an annealing
at 200°C for 2 hours, the top silicon wafer was completely
removed down to the oxide and the oxide was etched away to access
the copper pads. The contact resistance, Rc ,and the specific
resistance, rc, were calculated as 9.8 mΩ and 0.98
µm² respectively.These values are reported to be
similar to those obtained with thermo compression or Cu-Sn
interdiffusion.

These studies clearly show that 350
°C thermocompression bonding is not necessary to bond highly
polished copper surfaces. We also need to keep an eye on
delamination at the TiN / SiO₂ interface during the
bonding process.

RTI
International

Alan Huffman and co-workers from RTI
Int have continued their studies on copper –tin solid liquid
interdiffusion bonding. RTI contends that when bonding two chips in
face-to-face configuration, the choice of the bonding metallurgy is
likely to be dictated by the device surface topography and the
temperature limitations of the device. That is to say that the
bonding yield of rigid bump structures is critically dependent on a
number of factors, including the intrinsic flatness of the device,
the degree of planarity that the devices can be aligned to one
another, and the bump height uniformity. The use of Cu/Sn bumps can
provide compliance for the bonding process, allowing compensation
for small height variations arising from these factors and
resulting in a high bonding yield.

The lower sensitivity of the
Cu-Sn-Cu bonding process to the surface topography and/or flatness
is due to the bonding mechanism in which Sn is heated above its
melting temperature (232°C) and wets the Cu metal pad on the
second chip, leading to bond formation through solid-liquid
diffusion. Since the Cu-Sn-Cu bonding process is executed at
temperatures as low as 275°C, Cu-Sn-Cu bonding consumes less
thermal budget and subjects the bonded structures to lower thermal
stresses than would Cu-Cu thermocompression bonding. But, since
Cu-Cu bonds contains only Cu and no intermetallic phases, one would
presume them to be mechanically stronger than the Cu-Sn-Cu bonds
which contain Cu₆Sn₅ and Cu₃Sn
intermetallic phases.

Die shear measurements on 50 um
pitch Cu-Sn-Cu bumps [275°C, 100 MPa pressure, 3 min] vs Cu/Cu
bumps [300 °C, 340 MPa, 15 min] revealed Cu-Sn-Cu failure at
the Ti-SiO₂ interface and individual shear strengths
ranged from 42 to > 114 MPa ( non equal presence of the
intermetallic phases ??). Cu-Cu shear strengths all exceeded 114
MPa. During Isothermal aging ( 500 hrs at 150 °C ) the shear
strength of the Cu-Sn-Cu interface actually improved. It is
proposed that this is due to conversion of the more brittle
Cu₆Sn₅ to the more stable
Cu₃Sn.

Tohoku
University

Koyanagi-san and his co-workers at
Tohoku Univ have been studying 3D Integration for over two decades.
In their most recent work they are addressing the issue of
die-to-wafer (D2W) bonding time and its impact on the overall cost
of 3D processing. Their solution is to pick up multiple KGD using a
ceramic vacuum chuck (see fig below), rough align them to their
stack positions and then use liquid surface tension ( fluidic self
assembly) to pull the die into exact alignment as is shown in the
schematic below. This is the exact same technique that is used to
align bumped die on substrates (using the molten solder as the
liquid). An “aqueous liquid” is used on the hydrophilic
bonding area. For 5 mm chips, final alignment accuracy is between
100 and 600 nm. Work is ongoing on this area.

For all the latest on 3D IC
Integration stay linked to Perspectives From the Leading
Edge……………………………..