3D IC at the 2009 ISSCC contd.

February 25, 2009

continuing coverage of the key 3D IC
papers at the 2009 IEEE ISSCC………….

Toshiba

We have already discussed how
Toshiba’s commercialization of CMOS CIS with TSV launched this
industry segment [ PFTLE , “Imaging
Chips with TSV Announced for Commercialization”,
10/27/2007; “Toshiba
CIS Camera Module Details, EVG & 3M Settle”,
12/22/2008 ] Toshiba has also made it clear that 3D stacking with
TSV will be necessary to maintain and increase performance in high
speed memory ((DDR3 and above) .

At ISSCC the University of Tokyo and
Toshiba jointly presented a 3-D integrated solid-state drive (SSD)
that addresses what they called the key design issue for SSD
development - decreasing power consumption. The solution was a
stack of NAND flash chips, DRAM, a NAND controller, and a new
low-power voltage generator. In this application, the 3-D
integration lowers power consumption, because of its a short
interconnects. This program is certainly in R&D.

Taking a look at the Toshiba roadmap
for SSD products ( below) some marketing types out there are
interpreting the label “stack technologies” to mean 3D
integration. I do not. To me this is the same “3D stacking
that is available on todays DIMMS where peripheral I/O are
connected together – nothing more. As evidence I offer that
you can buy 512 Gb SSD today from Toshiba and they most certainly
DO NOT contain TSV…..YET.

Samsung

Last year at ISSCC, Samsung
described a 45 nm 4 Gb NAND flash memory with two 3D stacked memory
cells. They adopted a shared bitline structure so that the upper
and lower cells could share the bitline switch and the page
buffer.

This year in the paper entitled
“8 Gb DDR3 DRAM Using TSV Technology” Uksong Kang and
co-workers described the use of 3D TSV stacking to overcome future
DRAM performance issues.

They state “Currently, in
order to increase memory module density, more thinned DRAM chips
are simply added and their leads connected. However, this results
in increased power waste due to duplication of circuit components.
However, this limits the input/output (I/O) speed since increased
channel loading causes degradation in signal integrity. To overcome
the I/O speed limit, several buffered module solutions have been
proposed, where data pins are buffered by additional chips.
However, this increases power consumption and latency,
significantly. 3D DRAM with TSVs overcome the limits of
conventional module approaches.” The 3D DRAM supports a
single master and three slave chips connected using about 300 TSVs.
I/O data rate to increase to 1600Mb/s, while it is limited to
1066Mb/s in conventional quad-die package (QDP) structures. Power
can be reduced by 50% compared to non TSV chip stacking since
redundant circuits, including delay-locked loop (DLL), input
buffers, and clock circuitry, are eliminated. TSVs add latency of
one clock cycle at 1333Mb/s. This latency increase, however, is
small compared to the 3 or 4 cycles added in other buffered module
solutions.

The presence of redundant TSVs is
found to increase yield. For example two additional TSVs per 4
signal TSV group provides assembly yield of >98% for 300 TSVs.
The chip area overhead due to the redundant TSVs is 0.3% and 0.6%
for 40μm and 60μm pitch, respectively.

No announcement on commecialization
date was made.

Lincoln Labs

We have gone over the logic of CMOS
image sensors (CIS) leading the way for 3D technology many times. [
PFTLE , “…on
Mechanical Bulls, Rollercoasters and CIS with TSV”,
09/24/2008 ] and the reasoning behind the coming changeover to back
side illumination [ PFTLE “Backside
Illumination (BSI) Architecture next for Next Generation CMOS Image
Sensors “, 08/03/2008 ]

At ISSCC this year, Suntharalingham
from Lincoln Labs presented a paper entitled “ A Four Sided
Tileable Back Illuminated, 3D Integrated MPixel CMOS Image
Sensor”. For the applications they are examining such as
wide-area persistent surveillance, reconnaissance, and astronomical
sky surveys they require “…simultaneous near-real-time
imagery with fast, wide field-of-view coverage”. Since the
fabrication of a complex large-format sensor on a single piece of
silicon is cost and yield-prohibitive and is limited to the wafer
size, many smaller-sized image sensors are tiled together to
realize very large arrays. They report the first back-illuminated,
1Mpixel, 3D-integrated CMOS image sensor with 8μm-pitch 3D via
connections. The layer layout is shown below along with a cross
section of the LL process done in their standard SOI 3D technology.
The 3D imager is a 2-tier 1024×1024 pixel image sensor array
fabricated with 8μm-pitch, per-pixel 3D vias. The imager is
vertically connected to the silicon stack through a gold stud bump
array at 500μm pitch. Tier 1 consists of 100% fill factor,
deep-depletion photodiodes, thinned to 50μm. Tier 2 consists of
SOI-CMOS pixel readout and selection circuitry that is 3D-connected
to Tier-1 photodiodes. The silicon stack includes 2 silicon chips
with 64, 12b pipelined ADCs, a timing sequencer, an image tile
address encoder, bias generators, an Inter-Integrated Circuit (I2C)
serial interface, and two 12b wide LVDS outputs. A 3D via connects
Tier-2 fully depleted SOI CMOS metal-3 to Tier-1 (diode) metal-3,
and a back-metal cap (BM-1) covers the 3D via plug.