3D Integration Stays HOT at Semicon West

There was significant buzz about 3D
integration at Semicon West.

Bernie Meyerson, VP of the Systems
& Technology Group in IBM, in his recent Semicon West keynote
presentation titled, “Semiconductor Technology: A Convergence
of Technology and Business Models”, indicated that silicon
technology and its business model are both in the process of making
dramatic changes because of, amongst other things, cost estimates
for developing the 22 nm node ranging from $2 to $2.5 billion. In
his concluding slide, Meyerson indicated that scaling as we know it
will be over in < 10 years but that advances will continue by
technologies like 3D IC integration. (a theme that we have
expressed before (see Perspectives From the Leading Edge [
PFTLE]- “Some
things need repeating” 9/29/2007)

SEMI® presented
it’s first annual “Best of West Award”,
recognizing important product and technology developments in the
microelectronics industries. The selection committee included
Bernie Meyerson, IBM, Pete Singer,
Editor-in-Chief, Solid State Technology, Francoise
von Trapp, Managing Editor, Advanced Packaging and
our own Laura Peters, Editor-in-Chief, Semiconductor
International.

The following 3D integration related
products / technologies were nominated:

• Alchimers eGViaCoat™ - for
  the electrografting of copper seed layers used for the
  metallization of TSV
• Aviza Technologies
  Versalis fxP, a single wafer cluster system integrating multiple
  processes for 3D-IC manufacturing.
• EVGs NanoSpray 150
  System - a fully automated high topography spray coating system for
  very small and deep patterns.

Alchimer won the
award.

Also at Semicon, Bill Bottoms and
Jan Vardaman assembled a 3D “panel of experts” which
included Bob Sankman from Intel, Lisa MacIlrath from R3Logic,
Clinton Chao from TSMC, Bob Darveaux from Amkor and John
Knickerbocker from IBM. Sankman offered that while Intel was ready
for the introduction of 3D integration, their suppliers were not. I
take this to mean that they cannot get 3D ready memory from their
suppliers yet. Any other interpretations out there ??. MacIlrath,
president of R3Logic, a design house focused on 3D integration,
fielded questions on whether the lack of standard 3D design tools
was slowing the adoption of 3D. Although some true 3D commercial
tools exist, MacIlrath said that there is a need to accelerate the
development of digital 3D IC design tools. She also said there is a
need to integrate existing 2D flows with 3D. Chao explained TSMCs
view that vias first technologies will be an integral part of the
IC fab process, and will achieve smaller geometries than other 3D
TSV options. Darveaux explained that vias first (either FEOL or
BEOL)will be done in the fab while vias last on the front side of
the wafer can be performed either in the fab or as an OSAT process.
Vias last on the back-side, however will be done after thinning and
therefore will be strictly a IDM or OSAT process.

Sematech conducted
a workshop entitled “Equipment Challenges for 3D Interconnect,”
during SEMICON West. Presentations were given by Qualcomm, EVG,
Accretech, Suss MicroTec, Sonix, NEXX Systems, and Applied
Materials.

AMATs presentation
by Sesh Ramaswami indicated that they too are now a believer in TSV
and 3D integration. Their approach to enabling TSV are shown in the
slide attached below. Basically offering etch, dielectric liner,
barrier layer and CMP unit operations and have a JDA in place with
Semitool on developments for copper plating. Of great interest is
one of their concluding comments that “ Preliminary analysis
(on the EMC3D 3D model) indicates that the transition to
smaller vias may be the quickest way to drive down the
total COO. Long time readers of PFTLE know that I have
been pushing for smaller vias and smaller AR for a long time now (
for instance see PFTLE “…If
its Thursday it must be San Jose” 6/8/2008 )

Also of great interest in the
EVG presentation by Thorsten Matthias was the
attached slide showing that polymer bonding (BCB) and Cu-Cu
thermo-compression bonding requires 4 bonding process chambers (for
throughput) and that the best throughput is achieved by oxide
bonding. They conclude that oxide bonding is today 35% more
accurate and has the best potential for future improvement and
provides a 10X faster process ! This has been the position taken by
Ziptronix ( for instance see PFTLE “Road
trip continued” 5/28/2008 ).

Oxide bonding appears to be picking
up steam and will be discussed more in future blogs.

For all the latest on 3D IC
Integration stay linked to Perspectives From the Leading
Edge [PFTLE]……