TSMC Roadmap, DRAM Timing and Sematech Highlights

The Semiconductor
International server told me that this is blog # 50 of
Perspectives From the Leading Edge [PFTLE]. Since
readership continues to grow, I can only assume my focus on 3D IC
integration (for the most part) meets with your approval. Hopefully
the information that’s shared here is helping you stay on top
of this rapidly changing area. Thanks to Semi Int for supporting me
in this effort and you, the readers, for coming back every week to
these pages.

Before I get to the promised review
of last months Sematech 3D IC workshop, I will share some new
information on some past topics.

TSMC Roadmap

In the past we have mentioned the
TSMC “roadmap” for TSV. [ PFTLE
“Foundry
TSVs are a comin’ – TSMC makes a play for a bigger
portion of the pie” 5/2/2008 ] I asked whether any of you
readers had a copy of it and one of you finally came up with it for
me. Below is the same roadmap that TSMC shared at the recent
Semicon West meeting. “IT17” will be their vias first
technology which they indicate would initially be made available on
17 um pitch. The PT 140 and PT 60 generations are vias last
technologies, so we can safely assume that the vias first
technology is not ready yet. This matches information that PFTLE
has gotten that TSMC is still looking at vias first options and
deciding on the best way to go. Since the technology decision has
not been made yet, I would not be surprised to see this pushed back
to 2012.

More on Memory

Secondly, the site
DRAM exchange has just (Oct 21^st) posted some
important info tied to last weeks blog [ PFTLE “
Memory
Market Headed South…Will SSDs Lead the Recovery ?” Oct
19^th 2008] .

The following are key points as to
when DRAM will move to TSV stacking:

• Intel 45nm CPU “Nehalem” (Core i7) will release in
  November of 2008
• Current North Bridge & P45 chipsets allow PC makers to
  choose DDR2 or DDR3 and most users have chosen the lower cost
  DDR2
• Core i7 will support only the DDR3 standard which will provide
  a strong push for DDR3
• but….Core i7 initially will be positioned for high end
  products and, DDR3 penetration in DRAM market will thus be
  limited
• Market should begin to adopt Core i7 in late 2009, but the
  economy will probably delay this into 2010
• Adoption of DDR3 will depend on the price difference between
  DDR3 and DDR2 not when DDR3 chipsets are made available

As you may recall from previous
blogs [ i.e. PFTLE “Road
Trip Revelations” 5/18/2008] when signal speed
requirements of 1333 and 1600 Mbps for DDR3 and DDR4 are reached
current packaging will not be able to deliver. So, it looks like my
projection that 3D TSV DRAM will start (note I said start and not
some double digit penetration of the DRAM market) sometime in 2010
has some support.

Highlights from Sematech
Workshop

Now some highlights from the
Sematech workshop “Manufacturing and Reliability Challenges
for 3D ICs using TSVs” which was held Sept
25^th-26^th in conjunction with the Advanced
Metals Conference.

“Unfluorinated MO-CVD
Cu Precursors…” – Air Products

The use of OMCVD precursor for Cu
seed deposition in 3D IC technology has been described previously.[
for example see P. Ramm et. al. “Interchip Via Technology by
Using Cu for Vertical System Integration”, 2001 Adv. Metals
Conf.] . The organometallic precursor material is usually
Cupraselect™ from Air Products [(hfac)Cu(VTMS), where hfac =
fluorinated beta diketonate functionality and vtms =
vinyltrimethylsilane ] or Gigacopper™ from Merck
[(hfac)Cu(MHY) where MHY=2-methyl-1-hexen-3-yne ]. While the
technique produces highly conformal and excellent resistivity
copper seed, it is generally viewed as suffering from the high cost
of the deposition equipment, the slow deposition rates and the high
cost of the OM precursor materials.

The Air Products group in Carlsbad
CA points out that the fluorinated groups in both of these
precursors : (a) cause unnecessary cost, (b) could cause adhesion
issues due to the heavy fluorine content (think Teflon) and (c) can
at most result in 50% copper deposition yield because they are
based on disproportionation reaction chemistry [ 2Cu(+1) → Cu
(metal) + Cu (+2) ] .

To overcome these issues they have
developed a new precursor, “K15”, which is non
fluorinated and can deposit 100% of the copper it contains, since
it’s deposition is based on reduction chemistry. I’ll
spare you the chemical structure. A liquid at 65 °C it results
in a high VP of precursor and is reduced by formic acid in the feed
stream. At 250 °C copper can be grown on TiN at 150 nm/min
.

For those who are looking at OMCVD
Cu in their 3D IC process, this is probably worth a look.

“….TSV
Metallization based on Electrografted Copper…”
Alchimer

Alchimer certainly has gotten their
share of hype recently for their electrografted Cu technology [ see
PFTLE “3D
Integration Stays Hot at Semicon West”, Aug
13^th 2008 ] . Alchimer, which spun out of CEA Leti
several years ago, is a “develop and license”
technology company. Their Cu seed deposition technology “eG
ViaCoat” is based on a biased surface initiating
“grafting” to semiconducting surfaces surface. The
copper (as shown in the figure below) is highly conformal and has
no trouble coating very high aspect ratio vias. As you know
I’m not a fan of the high AR vias (for the next 5+ years),
but I see more applicability for their technology package than just
high AR vias.

For eG ViaCoat they have shown low
copper resistance and compatibility with standard electroplating
processes and CMP processing.

Alchimer quickly understood that a
technique to deposit Cu seed was of limited value if the
practitioner still had to deposit TiN barrier/adhesion layer by
another technique. Alchimer has thus developed a barrier deposition
process [ “cG” – for chemical graft ] to
compliment their copper process. The latter is expected on the
market in 2009. To take things one step further, and lock up the
whole via filling process, they have also developed a chemical
graft insulation process. Their full via fill process is known as
“AquiVia” I think this overall process can have
potential impact on generic TSV filling irrespective of aspect
ratio. Having said that I’d like to see more information on
the composition of the insulation layer. From the description of
the chemistry I have to assume that this is an organic layer, and ,
as such, I have questions on thermal stability, metal migration
etc. that I will try to answer for you in the future.

“High Speed Copper
Filling….” - Ebara

Ebara, a Japanese giant in
electroplating technology, gave a nice presentation on their copper
plating technologies for TSV filling. An interesting plating time
vs via size slide from their presentation is shown below. Although
this should be intuitive, it clearly shows that for a given via
depth the larger via diameters take longer to fill.

“Die Cavity
Integration for TSV Stacking” IBM

We have seen the use of a template
to help speed up die to wafer 3D IC assembly before [ PFTLE
“ 3D
Road Tour contd”, May 28^th 2008 ] from
Tezzaron.

In this presentation by IBM Tokyo
Labs, we see the possible next level of integration where several
die are stacked in a template and bonded all at once ( see fig
below). Very clever idea, for which I’m sure they have filed
for patents !

For all the latest on 3D IC
Integration stay linked to Perspectives From the Leading
Edge……………