Like Swallows Returning to San Juan Capistrano
The
“miracle of the swallows” takes place each year at the
Mission San Juan Capistrano in CA. Each year on March
19th the little birds are drawn back to
their summer home where they rebuild their mud nests, which
cling to the ruins of the old stone church . Visitors from all
parts of the world gather to witness the return of the swallows.
“Scout Swallows” precede the main flock by a few days to prepare
the way for the main flock to arrive.
In similar
fashion 3D IC practitioners assemble each year, in mid March, at Ft
McDowell AZ for the annual IMAPS Device Pkging Conf (DPC). They are
preceded, by a day, by the marketing and sales folks (scout
swallows) who attend the IMAPS Global Business Council
(GBC) to discuss the present and future of 3D IC from a
commercialization standpoint. [ For last years coverage see PFTLE,
“3D Practitioners Assemble at Ft McDowell”, 03/23/2008
& “More 3D IC Integration from Ft McDowell”,
03/30/2008]
Despite the current economic upheaval and
resultant corporate travel restrictions the 2009 IMAPS DPC/GBC
drew 500+ attendees to hear about the latest technical
achievements in 3D IC, WLP,MEMS and
LEDs. For the
next few blogs I will be covering what I felt were some of the new
/ key technical topics that were covered by speakers last week,
especially in the 3D sessions.
On
Tuesday night we held a panel discussion on the key
commercialization questions for 3D. That material is covered under
a separate web article “IMAPS panelists address tough 3D
Challenges”
[www.semiconductor.net/article/CA6645248.html?desc=topstory].
During day 1 of the regular sessions, Rosalia
Beica of Semitool, who we interviewed a few months ago for PFTLE [
PFTLE, “3D IC Questions and Answers with the EMC-3D
Consortium’, 10/04/2008] gave the audience an update on
the activities of the EMC3D consortium. One of the interesting
things I saw was the attempt to use W as the barrier / seed layer.
Paul Siblerud later added that while W does function as a good
barrier he thinks its only being used by companies who have that
technology available in R&D …He believes TiN or perhaps
Co will be the winners in the long run.
The
next slide represents a look at via costs by their 3D IC COO
software. As I have
been preaching for the last year and a half, the lowest cost of
ownership and best throughput comes from small vias with low aspect
ratios. Nice to see the
numbers agree with my preaching ! All the vias are filled with Cu
and the slide assumes a full Cu fill even for the large vias. The
liner in all cases is SiO2 and the vias have a TiW barrier and a
900 A Cu PVD seed layer. Notice how the smaller vias really pump up
the wafers / hour, i.e throughput !
In
early 2007 EMC3D projected a COO of $412 / wafer on a capital base
of $142MM. In late 2008 they announced that they had lowered the
cost to $108 / wafer based on capital of $108MM. Their goal
for 2009 is to reduce COO to $145 / wafer and capital to $80MM.
These are some major reductions in Capex and COO. A few more cycles
and we should be ready for production.
Below is the most recent COO run for 5 x 30 um
vias (although I would prefer to see 5 x 20 for the reasons
mentioned above). Siblerud indicates that this COO assumes bonding
is with 30 um dia micro lead free bumps on 80 um pitch and a 5 um
Cu RDL.
Paul Sibelrud as part of his Semitool
presentation showed a slide from Kaist which points out the
noise coupling Issues in TSV based devices. No major problems
yet, just pointing out that you need to keep an eye out for such
electrical issues.
Bob Patti of Tezzaron, a
pioneer of this technology , points out that he has been at this
for about a decade. In the slide below he indicates that to him,
the “killer app” will be memory on logic
because of the access time / latency issues we have discussed in
the past. The second slide shows a mock up of a device they are
prototyping for a customer. There are 4 512Mb devices attached to a
multicore processor. The memory chiplets are bonded
exactly where they are needed on the processor chip.
Tezzaron’s latest qual data is shown on the 3rd
slide . They are seeing 3D interconnect failure in the 10 parts per
billion range.
More updates from IMAPS DPC 2009 coming next
week
For
all the latest on 3D IC technology stay linked to
PFTLE……………………….
