3D IC Integration at the 2009 IEEE ISSCC

Information
Overload

Before I fill you in on 3D papers at
IEEE ISSCC (Int Solid State Circuits Conf) lets talk about
information overload. Several of you have contacted me by e-mail
suggesting that I index these blogs so you can access the
information. Certainly searching through all the PFTLE blog titles
is not the way to do this. I brought this issue up with
Editor-in-Chief Laura Peters and she quickly pointed out what
should have been obvious “… that’s what the search
engine is for in the upper left hand corner where is says powered
by Zibb”. Sure enough it works. Please give it a try. What I have
not been consistent enough about is using the acronym PFTLE in
every blog (especially the early ones) so I promise by the end of
Feb., to go back and make sure PFTLE is a key word in all 64 of
these so you can then find what ever your looking for by putting in
PFTLE and the topic.

Int Solid State Circuits
Conf

The Feb edition of IEEE Spectrum
magazine announced that “Chipmakers are officially headed
into the third dimension” but as a reader of this blog you
already knew that. What they were basing this headline on were the
papers recently given at the 2009 ISSCC conference. Trying to keep
you up to date, here are what I consider were the significant 3D
presentations at this meeting.

NEC

NEC has been very active in 3D IC
integration in the past few years detailing their vias first
technology which uses poly silicon to fill the vias [”Posturing and
positioning in 3D ICs”, Semi Int, April 1st 2007] In their new
presentation “A Chip Stacked Memory for On Chip SRAM Rich
SoCs and Processors” NEC details their rational for memory on
logic 3D Integration which they are calling “chip stacked
flexible memory” They are focusing on memory for SoC but this
really is simply another chip-on-chip (CoC) configuration for
memory on logic (Can someone please explain to me why each company
needs to reinvent names for things that already exist ?) For
example, they pint out that each functional IP core including 3D
graphics and video codec can be connected to closely positioned
local memory for fast access and wide bandwidth.

They indicate that their previous
designs use a multilayer bus and an MMU for each IP core on the SoC
chip to improve the efficiency of the use of the external memory.
However, due to high access latency and narrow bandwidth, this
architecture limits the potential for replacing IP-core local
memories with external memory chips. To avoid this limitation, they
develoed a CoC 3D integration configuration. They claim that the
memory can be stacked on any type of SoC chip.

They also developed high-density
(10μm pitch) inter-chip “electrode” technology to
replace their existing 50 μm pitch micro-bumps interconnect
technology. These small connections can provide direct access from
each IP core in the SoC chip to a localized memory area in the
memory chip. When such a memory chip configuration is used with a
mobile phone SoC chip, 50% of the on-chip SRAM of the SoC are
eliminated.

The fig below shows a micrograph of
a memory-chip prototype having 4×8 MEs (memory elements)
fabricated in a 90nm process. On the chip surface, Cu studs with a
thin Au cap are formed for I/O pads. Matching 5 mm square and 10mm
pitch copper pads are located in ME-interconnect logic areas.
“…the high density of electrodes provides 16 I/O
blocks, resulting in highly parallel access, using a maximum of 32
channels from an SoC chip. The maximum inter-chip memory bandwidth
is 8GB/s at an operating chip frequency of 125MHz.” No
indication of commercialization timing was given.

Infineon

As you may recall Infineon, working
with Fraunhofer IZM-Munich, was one of the first companies to
attempt commercialization of 3D Integration with a chip-on-chip
based smart card controller device in 2004. While that device never
reached full commercial production, they have continued to look for
opportunities to use this technology. Werner Weber, of Infineon,
indicated at ISSCC that 3D TSV are being examined for use in tire
pressure monitoring sensor devices (fig below). This wireless
device can sense pressure, inertia, and temperature. The stack
contains a micro electro mechanical sensor, a power-supply module,
a microcontroller, and a transceiver as shown in the figure below.
The transceiver and the tire-pressure sensor have TSV connections.
While the current commercial device contains no 3-D technology,
Werner indicated that the device presented at ISSCC could possibly
become the second generation “tire sensor”
technology“…with a little more R&D” .

I’ll finish off the ISSCC 3D
theme early next week looking at Toshiba, Samsung and a new BSI
CMOS CIS (keep up on your acronyms !) by Lincoln Labs.

For all the latest in 3D IC
integration keep linked to Perspectives From the Leading Edge
[PFTLE]
……………………..