3D IC at the WLP Conference

3D IC has now penetrated the WLP
(Wafer Level Packaging) Conference which SMTA holds each fall in
San Jose. To be fair, since all the key players in CIS (CMOS Image
Sensor) technology have adopted backside TSV [ see our last
discussion in PFTLE “…on
Mechanical bulls, rollercoasters and CIS with TSV”,
9/26/2008] and backside wafer level redistribution there is
certainly overlap here. Indeed the current CIS packages are
wafer level packages.

Brewer Science /
EVG

Brewer Science gave an update on
the temporary bonding technology that they have developed with
EVG. It is now pretty generally accepted that spin-on temporary
adhesives such as Brewers WaferBond™ HT materials are more
thermally stable, offer better planarization of surface topography
and better protection of wafer edges during the thinning process
than their less thermally stable tape counterparts.

In their paper, Brewer / EVG
offer two debonding options: (1) debond, clean the thinned
wafer and transfer to film frame for dicing and subsequent C2W pick
and place (p&p) or (2) W2W bonding followed by debonding of the
carrier. Depending on process requirements like adhesive
thickness and wafer topography, they claim it is possible to debond
the wafers at temperatures between 190 and 220 C on the EVG
tool.

PTFE, being a proponent of
C2W, especially in the early stages of 3D IC technology,
 prefers transfer of the temporary bonded wafer to the film
frame, sacrificing the carrier wafer by dicing the bonded pair, C2W
p&p and then solvent removal of the carrier from the
transferred, though not yet “bonded” die. Since I think
it is favorable to go as thin as possible, vs high AR via drilling
and filling, [ see PFTLE “If Its
Thursday this must be San Jose” June 8, 2008 and
“ASET
Drives 3D Integration….” June 21, 2008 ]  and
since reliable thin full wafer handing is difficult ( think about a
10-20 um thick, 300 mm wafer), this, to me, appears to be a
better approach and does not appear to require significant changes
in the Brewer / EVG proposal.

Balzers

We haven’t seen Balzers, an
old timer in the metallization arena, address 3D technology until
their paper in the WLP Conference. They looked at several highly
ionized plasma vapour deposition  techniques for conformal
barrier and seed deposition in high AR vias. Again I offer the
caveat that going thinner results in lower AR vias and eliminates
this problem somewhat, but for those committed, for what ever
reason, to high AR vias, such techniques will be necessary. The
deposition of a Ti barrier layer, shown below, shows that while the
coverage certainly is not conformal in these high AR vias (10:1
– 30:1) it is continuous. Balzers  points out that
continuity is achieved as long as the scallop of the DRIE etched
sidewall does not exceed 200 nm.

For copper seed deposition, which
cannot reach the same degree of ionization as Ti, the coverage is a
little worse.

CEA Leti

Leti researchers presented some nice
detail on the technology required for backside TSV on CIS. Their
backside TSV design requires 4 lithio steps ; double sided lithio
for the vias to the back of the front side pads; via metallization
and backside metal routing; metal passivation and UBM.

The overall process is shown in the
figure below. Their study of via insulation was described as a
tradeoff between low deposition temperature and conformality of the
deposit. They used a low temp PECVD SiO2 ( SiH4 + N2) deposited in
an STS tool. Deposition was done at 250 nm/min at 150 C. Since it
is well known that dep temp controls density and density effects
the breakdown voltage of the oxide, it would be nice to know the
electrical performance of this deposition. Back side processing was
done with DuPont dry film [ see PFTLE “ST
Micro announces more CMOS Image Sensor Capacity with
TSV”, March 5, 2008] instead of liquid resist to
eliminate the need to subsequently remove resist from the via hole.
DuPont MX5015 gave them 10 um resolution. BCB was used as metal
passivation.

Vertical
Circuits

Vertical circuits (VC) has been a
proponent of 3D stacking by edge connection, a similar
approach to that of Irvine Sensors in the US and 3D+ in
Europe. For CIS packaging VC is proposing offset stacking followed
by Parylene insulation, patterning and connecting with a silver
filled polymer (epoxy ??) which is deposited and subsequently cured
to a glassy state. They indicate that high speed jetting can be
used to deposit the conductive polymer. VC is showing prototypes of
this technology for stacked memory as is shown in the figure
below. 

Stay linked for updates on the RTI
global 3D Conference later this week

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technology and commercialization stay linked to Perspectives
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