Elpida Changes DRAM Capacitor Technology
As a break from the hyper-intensity of our Intel 32-nm analysis, I was scanning through some of the other chips we have been looking at recently. A couple of images caught my eye, without really knowing what they were:
Without thinking about scale, what could we be looking at? A bunch of drinking straws? Some of those weird worms by the volcanic vents at the bottom of the Pacific? Of course, we know that we’re dealing with a chip, and the only chips with tubes in them that I can think of are fluidic MEMS devices, DRAMs, and the nanotube R&D devices that show up at the nano-conferences on a regular basis.
We haven’t seen any fluidic MEMS chips here yet, so in the real world it has to be a DRAM, and that’s what it is - we’re looking at the top of the capacitor array in an Elpida EDJ1108BASE 1-Gb DDR3 SDRAM, fabricated in their 70-nm technology (we did a process node analysis of it back in the spring). Here we are looking at a cleaved section which has broken unevenly, exposing the tops of some of the cylindrical capacitors embedded in an oxide matrix.
The process uses six layers of metal in total, three copper and one aluminum above the array, and tungsten is used as the capacitor top plate and metal 2, and as bitlines below the capacitors. A conventional section is shown below, parallel with the bitlines. On the right is the edge of the capacitor array, and we can see the almost 15:1 aspect ratio of the individual 2.65 µm tall cylinders.
In the cleave images, one thing that stands out clearly is that the capacitors are hollow - no more hemispherical-grain polysilicon to increase the surface area. To make sure this was not an artefact of our sample preparation, we did a bevel polish from the top down, and when we get to the capacitors we see that they are indeed hollow:
Which implies that a high-k dielectric has been used, to keep the cell capacitance up; in fact, when we look at the capacitor structure we find that we have a complete change from the time-honoured poly/oxide/poly sandwich.
The TEM cross-sectional image below illustrates what the actual structure is at the top of a capacitor. Both conductive plates of the capacitors are titanium nitride (TiN), and the dielectric in between is a hafnium oxide (I won’t say it’s HfO2, because we haven’t done the quantitative analysis to confirm that). The tungsten layer on the top reduces the resistance of the top plate, and also acts a second-level interconnect for the device.
It’s been a while since I looked closely at DRAMs - I had assumed that the process shrinks would be more evolutionary and that not too much would change, aside from the amazing lithographic performance to generate the line density in the latest memory chips. Turns out I was wrong!
Einstein commented:
The capacitor is actually a depletion mode MOSFET. go to www.keystonesemiconductor.com for more info.
Xprmntl commented:
This information regarding the likely dielectric stack is readily available on line. At 70nm, the capacitor stack is probably an MIS stack, which would likely be TiN/Ta2O5/Si. For subsequent shrinks, stacks like Al203/HfO2/Al2O3 and ZrO2/Al2O3/ZrO2 are being reported in the literature and press releases.
Xprmntl commented:
Regarding die size. When shrinking the minimum feature size, the diameter of the capacitor stucture must follow suit. However, the capacitance needed for sense remains roughly the same, so the capacitor must be taller for the same K value. At 70 nm and below using Poly Si, that requires capacitor structures that are >2.5 um tall, which is very, very, very hard to do with dry etch Moving to a higher K dielectric provides the ability to go to a shorter capacitor structure. Each design node needs a higher K material, and/or a taller capacitor.
v8s6c commented:
Please help me to give me some topic to be research in my thesis on semicon technology,
paul commented:
well done,
could you please advise me what does such technology impact on the shrinkage of die size ?
