Inside the Numonyx PCM Chip
Images are the star of Chipworks Inside Angle, a new blog edited by Chipworks’ blogger-in-chief Dick James, senior technology adviser. These entries will sometimes deliver more in-depth analysis on major industry milestones, but the main focus is about high-magnification microscopy of the latest and greatest technology, reverse-engineered in Chipworks’ labs.
Inside the Numonyx PCM Chip
By Rajesh Krishnamurthy, Process Analysis Engineer, Chipworks
The long-awaited phase-change memory (PCM) by Numonyx is here in the Chipworks labs. It promises to be a significant step forward in the quest for next-generation memory, delivering at-par or better performance than flash memories, while being scalable with advanced CMOS. We are analyzing the chip to determine the PCM cell structure, layout and integration into a standard advanced CMOS process.
Intel Corp., in joint collaboration with STMicroelectronics, developed the PCM and transferred its technology, along with flash memory product lines, to the newly formed company Numonyx on March 31, 2008.
PCM combines the non-volatile attributes of flash memories like NOR and NAND-type, with bit alterability and the fast read/write times of RAM or EEPROM. This positions PCM to potentially provide memory subsystem solutions for cellular phones, PCs, and embedded and consumer electronics applications.
PCM, unlike flash, does not need a separate erase step. It can be read directly from memory with fast access times like NOR flash, and with read bandwidth similar to DRAM. PCM is likely to achieve write speeds >108 write cycles, like NAND flash, but is currently unable to match the write speed of RAM. This might be possible through PCM cell shrinks.
The added advantage of PCM memory (Table 1) is its long-term scalability with technology node, which is projected to extend to the 5 nm node. This, along with the incorporation of multi-level cell (MLC) design, will reduce PCM costs, previously only realized by hard disk drives.
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| PCM vs. other leading-edge memories1 |
The Numonyx PCM chip we are currently analyzing is housed in a 56-lead TSOP, as shown in Figure 1. The PCM die (Fig. 2) measures 4.83 × 7.44 mm (36 mm2). Figure 3 shows markings on the die that point to the joint development of the PCM chip by Intel and STMicro.
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| 1. Numonyx’s PCM chip is housed in a 56-lead TSOP. |
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| 2. The PCM die measures 4.83 × 7.44 mm (36 mm2). |
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| 3. Markings on the die point to the joint development of the PCM chip by Intel and STMicroelectronics. |
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| 4. The PCM cell is formed by connecting the storage element in series with a selector device.2 |
The PCM cell consists of a layer of phase-change material, germanium antimony tellurium (GexSbxTey, GST), embedded in a dielectric structure and in contact with two electrodes. The GST material of interest to memory applications is the Ge2Sb2Te5 alloy, which follows a pseudo-binary composition (between GeTe and Sb2Te3). The memory bits are stored in the high (Reset) and low (Set) resistance states of the GST material. The high-resistance state is amorphous, and the low-resistance state is crystalline.2 One of the approaches to achieve the two states is by using a sub-litho contact heater contacting a planar GST. We are currently analyzing the PCM cell to establish the composition and structure of the GST alloy used for this PCM cell.
The PCM cell (Fig. 4) is formed by connecting the storage element in series with a selector device. The selector can be implemented with a PNP bipolar transistor, an MOS transistor, or diodes. For high-density memory, the vertical integration of a PNP bipolar transistor may allow for a more compact cell layout.2 A Chipworks analysis report will identify the type and structure of the selector device implemented in this chip.
The PCM cell, measuring 0.18 µm at its bottom and placed with a pitch of 0.44 µm from a neighboring PCM cell, is embedded within the pre-metal dielectric (PMD) stack of the die fabricated with four levels of metallization. Part of the general structure of the die, manufactured with a 90 nm process with the PCM cell visible, is shown in Figure 5.
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| 5. Cross-section of the Numonyx PCM memory array (length direction). |
The PCM memory cell size, visible in Figure 6, is 0.44 × 0.22 µm (0.097 µm2 or 12F2). The PCM memory cell size is ~30% larger than the 0.08 µm2 (10F2) cell size of a 128 Mb NOR flash cell (90 nm process).3 The PCM memory cell size is ~1.5× larger than the 128 Mb SLC NAND flash cell (90 nm process), and ~10× larger than a NAND flash cell from a 16 Gb NAND flash die (43 nm CMOS process). The Numonyx PCM cells are ~60% smaller than the smallest SRAM cells employed in the current-generation 40 and 45 nm chips.
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| 6. Plan-view SEM image of die de-layered to PCM memory level. |
It will be interesting to see if our analysis finds evidence of implementation of multibit (level) per cell (MLC) strategy in this chip. STMicroelectronics has revealed in an ISSCC Publication4 a multi-level programming algorithm based on the program-and-verify technique, with the aim to create stable intermediate regions of the cell. According to the paper, the chip can be embedded with a multi-level programming algorithm, which is capable of building intermediate states by properly initializing the cell to a known state, and then using the algorithm to make the cell gradually more conductive.
We are currently analyzing this chip in detail to answer some of these questions. But what we have seen so far is an impressive bit of process engineering (pun intended).
1. “The Basics of Phase Change Memory Technology,” Numonyx.
2. R. Bez, “Development Lines for Phase Change Memory,” Numonyx.
3. “STMicroelectronics Announces First 90nm NOR Flash Technology,” STMicroelectronics.
4. F. Bedeschi et al., “A Multi-Level-Cell Bipolar-Selected Phase-Change Memory,” 2008 IEEE ISSCC, Digest of Technical Papers, p. 428.
Stacey commented:
Nice work BHD.
diffusion commented:
The metal is an easier heat flow path than the neighboring track.
Since it underlies the neighboring track that is an advantageous
position.
Optimist commented:
Not sure I understand you there... if you're redistributing heat
across the entire reflective metal film of a [CD/DVD] disc, then
you'd disturb neighboring tracks. But that apparently isn't a
problem. We'll have to see about scaling, but smaller wires take
less current to heat, so at least the trend is in the right
direction.
Fred Chen commented:
Optimist, the heat dissipation should be through metal layers but
that does not bar the heat from moving between cells. The more
easily heat is dissipated the less efficient the PCM cell. The disc
has the entire reflective metal film to act as the heat
redistributor which you can't use with a cell array. PCM scaling is
limited by the driving current mainly.
Optimist commented:
Luckily, thermal conductivity of GST is low (near the theoretical
minimum for its atomic structure). Thermal conductivity of silicon
dioxide isn't terribly high, either, so the opportunity to disturb
neighboring storage locations is fairly minimal. Most of the heat
will be contained at the interface and dissipated through the metal
layers (where it won't do any harm). The fact that CDs and DVDs
work is testimony to the fact that neighbor disturb isn't an
insurmountable problem. IBM, in another paper, has said they see no
problem scaling PCM down to 2nm, and possibly beyond. They can't
have it both ways. (We'll see soon enough... isn't it about time to
start seeing 45nm parts?)
Skeptic commented:
A recent IBM presentation hinted strongly that the scaling issues
are much larger than originally anticipated. For a number of
reasons, sub-45 nm PCM will have the phase change material in a via
(rather than on top of a planarized heater plug). The huge
surface-to-volume ratio of the scaled cylindrical element will
allow all but a tiny fraction of the heat energy to escape and the
problem only gets worse as the element shrinks. This means that
scaling predictions based on the current Numonyx chip are highly
suspect (i.e., wrong).
Fred Chen commented:
If you have a GST cell programmed in the high resistance state,
cumulative exposure to high temperature (like 130 C or higher)
actually lowers the resistance because of cumulative
crystallization. This exposure could be from repeated programming
of adjacent cells, for example. GST peak programming temperatures
commonly exceed 450 C and the heat naturally diffuses away from the
heater to the next cell.
StatsMaster commented:
@Fred Chen: Acceleration factors will have to be independently
determined for each technology. For NOR or NAND, 180C may represent
(let's say a) 10x data degredation acceleration. We may find for
PCM that 180C represents 100x degredation acceleration, relative to
nominal use near room temp. In such a contrived scenario, the
real-world degredation of PCM might be considerably better than NOR
or NAND, despite its performing worse on a 180C stress.
Coulomb commented:
Two electrons squeezed closer together will try harder to pull
apart. Hence the lack of permanent charge storage. For different
numbers of stored electrons, the stored potential will be
different. It's a lot of variation, not even including the
contribution from charged impurities.
Ecd Fan commented:
So, it looks to me they sent you a 3-year old chip (based on the
2006 marking). Did you test that chip for write performance or
power consumption? If you had, you might have found out that it its
write throughput is SLOWER than modern NOR and its power
consumption in write is less than impressive! So, did you? The
conspiracy theory is, of course, that they intentionally sent you
an old chip - whatever problems you find, they will have an excuse
("but you were looking at a really old chip!"). When will Numonyx
publish a datasheet for the chip? Why is Numonyx so afraid to
reveal the true performance of its Alverstone? Are they afraid that
the technical community will finally know for sure that Phase
Change Memory is simply a techno-Ponzi, and nothing more. See
www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2009/02/is-phase-change-a-techno-ponzi.html
B S Krishnamurthy commented:
The phase changes are usually temperature dependent. In the device
the density of circuitry is so large that the heat removal is a
problem. Thus the phase changes may not be stable. Thus what may be
the temperature range over which one can expect stable phase.
Prof. B S krishnamurthy commented:
How sensitive is the phase change of GST?
NVM Expert commented:
"Well the heater is not heat-sinked perfectly... " Not sure what
this means. It is very important that the design rules are such
that cross talk does not happen. My point is that because the
amount of energy required to change the GST scales with the
technology, it's much easier to deal with then say managing <100
electrons on a floating gate.
crosstalker commented:
Well the heater is not heat-sinked perfectly...
NVM Expert commented:
Stress tests will clearly need to be modified. If the activation
energy for any failure mechanism can be obtained at lower
temperatures, which it can, then everything is good. Regarding
thermal cross talk, I heard yesterday at the IMW from Numonyx that
this is not an issue because the cell energy scales with the
geometries (meaning if it's ok today, it's ok tomorrow)
crosstalker commented:
Thermal crosstalk is also an issue. Let's say the heater of an
adjacent cell 20 nm away goes up to 500 C, isn't there a risk the
temperature of the unheated cell goes up significantly as well?
Fred Chen commented:
180 C is a stress test (among many). Some technologies do better
than others at this. You can't wait for the device to fail at room
temperature. My point is PCM is not the strongest candidate in this
area.
NVM Expert commented:
180C??? Who cares?
Rajesh commented:
I believe the chip is designed for op. temp from 0 to 70 C. I am
not sure what cell phone and similar applications, which I believe
this memory is targetted for will require transisor and memory
element operating at 180 C?
Fred Chen commented:
How long can this chip hold data for at 180 C? Not much.
