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IBM And The All-In Bet on High-K
October 6, 2008

The debate about the worthiness of high-k/metal gate technology brought to mind what Japanese semiconductor managers said about Hajime Sasaki, who ran NEC’s semiconductor operation back in the late 1980s. “He knows how to keep the fabs full,” they said.

 

IBM, with its “all-in” strategy for high-k/metal gate technology at the 32 nm generation, and TSMC, with its dual-track oxynitride and high-k/metal gate strategy, each are doing what they need to do to keep their fabs full.

 

Consider IBM, which spent a billion dollars over a decade of high-k development. The need for a replacement to SiON became apparent in 2003, when oxide scaling stopped at 1.2 nm effective oxide thickness (EOT). Current Intel 45 nm products with a  high-k/metal gate stack have an EOT of 1.0 to 1.1 nm, with a physical thickness of ~3.2 nm. By the 32 nm node, a leading-edge EOT will be 0.9 nm. It is worth recalling that at the 90 nm generation Intel’s microprocessors were panned for high leakage currents that put those Pentium CPUs outside their customers’ thermal envelopes.

 

Using high-k for its server microprocessors makes perfect sense for IBM. What about for its foundry customers? IBM’s Fab 323 runs 500-600 wafer starts per day, which translates to 18,000 wpm. The fab runs 80 active part numbers at any one time, with the “key clients” being the companies that use IBM-made video game processors and the IBM systems division itself.

 

That means that IBM must keep the cost of high-k low enough to keep the video game managers at Sony, Nintendo, and Microsoft satisfied. Silicon-on-insulator (SOI) already adds ~$500 to the wafer cost. Will the Fishkill alliance partners all be happy with an all-high-k solution at 32 nm?

 

A second question is whether the all-in high-k/metal gate strategy by the Fishkill Alliance will meet the needs of the foundry operations at Samsung Electronics Co. and Chartered Semiconductor Ltd. Samsung is in the process of ramping its S1 logic/foundry fab in Kihueng, Korea, which has a total capacity of 45,000-50,000 wpm. Chartered has a wide range of customers, and its Fab 7 to fill. Will these Common Platform partners be well-served by an all-in high-k strategy?

 

Walt Lange, vice president of platform alliances at Chartered, said the Singapore-based foundry will be taking to market 32 nm HKMG as “our go-to-market LP offering. Not only do we think it has compelling power/performance and leakage attributes but it is a very cost-effective technology.”

 

Rather than looking at oxynitrides as a more cost-effective technology than high-k/metal gate, Lange said “because we can eliminate the stress engineering by using HKMG, the technology is actually less complex” and thus cost-competitive.

 

“We'd also like to note that due to the lack of design impediments in HKMG, that are imposed when strain engineering is added to a technology, designers of cost-sensitive applications will find themselves with more design flexibility with 32 nm HKMG. When you compare to 40 nm offerings, we also drive the chip-scaling factor that will make this technology all the more compelling,” Lange said.

 

All of this depends on a third question: How big of a cost adder is high-k/metal gate technology? At the Sematech-organized International Symposium on Advanced Gate Stack Technology last week in Austin, Texas, one Sematech source claimed that a high-k/metal gate technology adds only $500 to the cost of a processed wafer. Two other sources said the high-k/metal gate cost adder is in the $1500-$3000 range for leading-edge processed wafers that cost ~$7000 at the leading foundries now.

 

ALD tools for the dielectric, and sputtering equipment for the metal electrodes, are costly compared with thermal oxide furnaces and CVD tools. At this early stage of the game, adding high-k can significantly cut yields, which of course raises the per-die cost. For TSMC, with ~$10B in revenues, going to a dual 28 nm offering is the only way to go if it hopes to keep its huge 300 mm fabs full. Offering high-k for MPUs, high-end graphics, and other performance-driven chips, and oxynitrides for the cost-sensitive baseband chips that can get by with a ~2 nm SiON oxide, is an obvious strategy.

 

Will high-k manufacturing costs come down quickly? Tokyo Electron Ltd. offers a combination ALD/CVD tool that uses ALD for the first few atomic layers, and then CVD to fill in the rest of the dielectric. Applied Materials Inc. is working hard on higher-throughput plasma ALD tools.

 

Already, some companies have gone down the wrong paths on high-k. NEC and Matsushita both tried to develop a low-power, low-cost solution that tried to marry a hafnium silicate with a poly gate. That ignored all the evidence about Fermi-level pinning with a poly electrode. Others tried to keep costs down by using a fully silicided (Fusi) process, an approach which ultimately was “deselected” by the semiconductor industry.

 

It will be fascinating to see how all of this plays out. IBM has placed a 32 nm high-k or bust bet that it can reduce the manufacturing costs and improve the yields enough to keep its fab full. Will Chartered, Samsung, and the other Fishkill Alliance partners be equally well-served by an all-high-k strategy?

 

After a decade of development work, a high-k/metal gate technology is ready, with higher performance, reduced leakage and (according to Sematech researchers) higher reliability than a SiON gate stack. Beyond IBM, Chartered and Samsung certainly have an interest in quickly improving the costs and yields. Then as now, chip makers need to keep their fabs full.

Posted by David Lammers on October 6, 2008 | Comments (0)