David Lammers

IBM@45: eDRAM, Si! High-k, No
June 27, 2008

It now appears that IBM Corp. plans to implement a high-bandwidth silicon-on-insulator (SOI) embedded DRAM (eDRAM) for its server microprocessors at 45 nm, and then introduce high-k/metal gate technology at the 32 nm node.

Gary Patton, vice president of technology development at IBM’s Semiconductor Research and Development Center (Fishkill, N.Y.) said, “We’ve done a lot of prototyping [of high-k] at 45 nm, and we are still assessing high-k for our systems business. For our systems [server] business, the focus at 45 is to get eDRAM into our technology because bandwidth is by far one of the most important technologies.”

At the 45 nm generation, Patton said IBM is able to meet its logic technology goals by implementing strain technology.  “Embedded DRAM was our No. 1 priority at 45, because high density memory on the same chip offers a very big performance advantage. Bandwidth is very important. For logic at 45, we get a very significant performance improvement with strain 
engineering. We are still looking at high-k/metal gates, and we are using 45 nm to assess the yield and reliability issues.”

The high-k effort has drawn a great deal of attention, including a front-page story on The New York Times in January 2007 when IBM, Intel, and Sematech all issued press releases about high-k development. It was clear then that Intel was ahead of the game, with working microprocessors that had high-k/metal gate technology at the heart of its Penryn chips.

As Gordon Moore said at the time, high-k/metal gate is a revolutionary change, and Intel deserves all the credit in the world for its high-k/metal gate introduction at the 45 nm generation. That said, embedded DRAM has an equally long technology development cycle, with IBM’s engineers working mightily to develop a built-in self test (BIST) solution, for example. And as important as transistor switching speed is, Patton is on the mark when he talks about the importance of on-chip bandwidth between logic and memory.

At several points over the last 18 months, IBM has said it would insert high-k at the 45 nm generation. IBM’s vice president of technology T.C. Chen put a great deal of pressure on himself and other IBM technologists to bring in high-k/metal gate technology at the 45 nm node. Apparently, they will get their satisfaction at the 32 nm generation, perhaps not quite as soon as they had hoped, but as Patton argues, soon enough. If the SOI eDRAM – which has a reported sub-3 nm access time – carries the water for IBM’s Power processors for awhile, that may be all right too. Innovation has many forms.

Posted by David Lammers on June 27, 2008 | Comments (0)