Link This |
Email this |
Blog This |
Comments (2)
SOI and the Fishkill Cosmology
January 2, 2008
It was nearly 10 years ago (August 1998) that IBM’s microelectronics division committed to silicon on insulator (SOI) technology for its high-end microprocessors. Last month’s announcement that Toshiba Corp. would join the bulk 45 nm Fishkill alliance reflects the shifting picture in silicon-on-insulator (SOI) development.
Toshiba was the “T” in ASTA, the AMD/IBM/Sony/Toshiba alliance which developed SOI technology. Now, the two Tokyo-based companies are out of SOI process development, and Freescale Semiconductor Inc. (Austin, Texas) is in, working on SOI development with AMD and IBM at Fishkill.
(Both Sony and Toshiba work with IBM on research issues related to future semiconductor technology, with SOI on the agenda of that alliance, which does work at both Albany and Yorktown Heights, N.Y.)
Sony has turned its leading-edge digital production fab in Nagasaki, Japan over to a joint venture with Toshiba. A Toshiba spokesman told Kenji Tsuda, Semiconductor International’s Tokyo-based contributing editor, that Toshiba has no plans to put in a 45 nm SOI manufacturing line in Nagasaki, due to the large investment involved and the disinclination by Toshiba’s top semiconductor managers to get into SOI manufacturing. The graphics processor “RSX” chip will be made in Nagasaki on a 45 nm bulk process.
That ends Sony’s foray into making some of the Cell Broadband Engine processors itself at Nagasaki, and consolidates the 45 nm SOI-based Cell BE production.
Meanwhile, a different source said Sony and Toshiba have signed on with IBM to explore development options for the 32 nm Cell Broadband Engine. That contract extends to January 2011 and is based on SOI technology, said the source, who asked not to be identified.
The Toshiba spokesman said Toshiba is using a bulk CMOS process to develop a Cell-based, simplified multicore processor called SpursEngine, which has four SPE (synergistic processor element) cores rather than the eight SPE cores in the Cell Broadband Engine. The SpursEngine chip, announced at Japan’s CEATEC 2007 show in October, has MPEG-2 and H.264 codec engines, an XDR DRAM interface, and four processor cores, designed for video processing with lower power dissipation. The chip will be used for facial recognition applications, among others.
What about the Cell BE? Is the Cell processor for the Playstation targeted at SOI in future process nodes? Bruce McConnel, the spokesman for IBM’s semiconductor operation, said in an e-mail exchange that “the value proposition for SOI technology in power and performance will continue to increase as we move to future technology nodes.”
While figuring out who is working with whom, note that IBM’s non-SOI process development has been much in the news lately. On the day after Christmas, Big Blue announced a deal to license its 45 nm bulk CMOS technology to Shanghai-based foundry Semiconductor Manufacturing International Corp. (SMIC), though IBM said SMIC will not join the Common Platform alliance supported by Samsung Electronics Corp.’s foundry operation and Chartered Semiconductor Manufacturing Ltd. (Singapore).
Also, a 32 nm test SRAM developed with IBM’s Fishkill alliance partners, with high-k metal-gate (HKMG) technology, was announced on Dec. 10th. The 32 nm SRAM was designed by engineers from AMD, Freescale, Infineon Technologies (Munich), Samsung (Seoul, South Korea), and — the most recent addition — STMicroelectronics (Geneva).
Interestingly, Toshiba is not on that list.
Posted by David Lammers on January 2, 2008 | Comments (2)
