David Lammers

IBM vs. Intel: High-k Innovation
August 6, 2007

The intensity of the Fishkill – Hillsboro rivalry increased markedly this year when dueling high-k/metal gate announcements from IBM and Intel came in late January.

Now a half-year later we learn that IBM has developed a “dipole” technology in its “gate first” high-k approach, while Intel is believed by many to have embraced a “gate last” approach which uses two different metals, one for NMOS and the other for the more-difficult PMOS transistors.

At the 2007 Symposium on VLSI Technology in June in Kyoto, Intel senior fellow Mark Bohr said another possibility is a gate first approach for the NMOS device and a gate last approach for the PMOS transistor.

Hints from Bohr are taken seriously. Details on Intel’s approach should emerge in December, when Intel is expected to present details of its high-k/metal gate approach at the International Electron Devices Meeting in Washington, D.C.

IBM adds a capping layer on top of the hafnium dielectric, a doping of lanthanum atoms at the NMOS side. To set the work function of the PMOS, the capping layer consists of aluminum atoms. By creating these capping layers between the high-k dielectric and the titanium nitride metal gates, IBM can avoid the more complex process of putting down two different metals.

One dielectric, one metal, but two different work functions, thanks to the capping layers.

According to sources at Semicon West, IBM’s approach appears to be significantly simpler than Intel’s, with at least three fewer process steps. At the VLSI symposium, IBM engineers presented a paper describing their NFET integration, and claimed a 5 nm reduction in channel length. In a veiled dig at Intel’s presumed Damascene approach, the IBM paper said any gate last Damascene approach would suffer from reduced mobility due to restricted thermal budgets.

The high-k competition extends the dueling approaches from these two companies over the last decade, with at least five places (including high k) where the two companies have diverged (3D through-silicon-via vertical interconnects may become a sixth).

IBM claimed in mid-1998 that it had moved ahead with silicon-on-insulator (SOI) technology. Intel spurned SOI as too expensive, and technically unnecessary to boot, with SOI’s slight advantage at 130 nm diminishing in the post-100 nm era.

Then Intel came up with “uniaxial” strained silicon for its 90 nm microprocessors, a true breakthrough. IBM later fought back with dual nitride stress layers, and then said it will introduce the Intel-pioneered embedded SiGe approach for its PMOS transistors at the 45 nm node.

IBM said it would embrace immersion lithography at the 45-nm node, claiming an advantage over Intel’s use of a double-patterned gate formation layer for its 45-nm silicon. Intel rebutted by saying it would have a cost advantage by using less expensive dry scanners at the 45 nm generation.

Early this year, IBM said it will incorporate a dense and fast form of SOI embedded DRAM, several times denser than SRAM and with sub 3 ns access and cycle times. Intel, which doesn’t use SOI, naturally said it could not endorse SOI eDRAM and was confident in its SRAM caches.

A few months ago, IBM surprised many when it would implement air gaps in the interconnect dielectric at the 32-nm node, based on a self-assembling polymer. Intel shot back by telling analysts that air gaps presented reliability challenges, and cost far too many masks to implement in an MPU interconnect stack.

This is an impressive rivalry, one that is driving innovation at a rapid pace for the entire industry. High-k appears to be an area where Intel is ahead in terms of insertion at the 45 nm node, but where IBM may have bragging rights about the more elegant solution, at least until the winter day when Intel speaks up at IEDM.

Posted by David Lammers on August 6, 2007 | Comments (0)