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TSMC and the Reverse Temperature Effect
April 30, 2008
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) held its annual technology symposium in Austin Tuesday (April 29), with much of the attention on the foundry’s 40 nm technology. TSMC would prefer that its leading edge customers go directly from 65 to 40 nm design rules, making 40 nm much more than an afterthought 0.9× linear shrink. In fact, TSMC will skip 45 nm and only offer 40 nm for the general (G) and (LPG) processes, with 45 nm and 40 nm offerings for the low power (LP) process which Qualcomm Inc. and others use.
J.C. Huang, platform marketing manager for TSMC’s advanced technology division, said in his presentation that there is no performance gain when migrating from the 65LP process to the 40LP process. Asking a rhetorical question of the 250 people in the audience, Huang said, “You say the same performance is not good enough, that I need more speed. Then we need to add three additional masks to enable the LPG process.”
During the coffee break, Huang qualified his statement that there is no performance gain when the low-power transistors shrink from 65 to 40 nm design rules. He clarified that there is no performance gain at -40° C, a 10% gain at 25° C, and a 17% gain at 85° C. The reason? A “reverse temperature effect,” Huang said.
Normally, CMOS chips run faster at cool temperatures. Huang acknowledged that the reverse temperature effect stands that on its head, with the 40LP process running somewhat faster than the 65LP process at 85° C, which he said is a typical operating temperature range.
To overcome the reverse temperature effect and get the performance gain that some customers need, the 40LPG process creates a thinner gate oxide (one extra mask), and adjusts the dopant implant profile (two masks). For chips aimed at 3G cellphones or video game chips where speed matters, semiconductor companies will use both LP and LPG transistors on the same die, he said. If the transistors use a 1.2 V power supply, the 40LPG process runs 20% faster.
TSMC’s situation reflects a much larger issue: simple shrinks no longer guarantee faster switching speeds. This was a major topic at the IEDM short course last December. M.I.T. professor Dimitri Antoniadis gave a detailed explanation of why CMOS devices may start to actually run slower starting at 45 nm compared with 65 nm, pointing to source injection velocity and other issues. At IEDM, Paul Packen of Intel Corp. described the danger of “diminishing returns” from scaling, particularly if oxide thickness is not reduced. MPU designers have talked about transistor variability in critical circuits causing inverse scaling, in which a 45 nm chip runs slower than its 65 nm predecessor. And random dopant fluctuations can easily ruin scaling’s benefits. If Vmin is stuck at today’s levels, said Intel fellow Tahir Ghani, scaling will face performance challenges.
And now we have the reverse temperature effect. To be sure, TSMC is moving aggressively to avoid inverse scaling. Huang said the 40G process coming to market this year includes a SiGe strained silicon module for the PMOS devices, which will be used in the 32LP process when it is introduced later this year. The 40G (the nomenclature used by TSMC now makes the G process the high-performance process for the 40 nm node) and 32LP processes also will include a dual etch stop liner (DESL). For the 32 nm node, the high-performance process aimed at CPUs will include a high-k/metal gate module.
Also, for the 40G and 40LP offerings, TSMC will offer embedded DRAM by the end of this year. In-process through silicon vias (TSVs) are planned with a 17 micron pitch.
All that said, the reverse temperature effect is evidence that shrinking linewidths is only half the battle to gain performance.
Posted by David Lammers on April 30, 2008 | Comments (0)
