As those of you who stay linked to Perspectives From the Leading Edge know, we try to stay on top of advances in the CMOS Image Sensor (CIS) market because this is viewed as one of the early adopters of 3D IC integration. We have described how key players such as Toshiba, Oki/Zycube, ST Micro and Aptina (Micron) have adopted TSV in order to offer the lowest cost / lowest volume cameras for cell phones. It is now clear that you’ll have to remember another acronym in order to stay on top of CIS technological developments and that is BSI – or- back side illumination.   

Smaller pixels result in higher resolution, smaller devices, and lower power and  cost. Shrinking pixel size in CMOS image sensors must be done without degrading performance or image quality. As smaller and smaller  pixels are fabricated on CMOS image sensors, however, the image quality is not improving.

OmniVision / TSMC

Towards the end of May, OmniVision announced that they solved the pixel size / image quality problem though backside illumination (BSI) technology. OmniBSI™ technology involves turning the image sensor upside down and applying the color filters and micro lenses to the backside of the pixels so that the sensor can collect light through the backside.

The reason for better performance with BSI is higher fill factor, the amount of light that can be collected in a single pixel. The various metal layers on top of a front-illuminated sensor limit the light that can be collected in a  pixel. As pixel sizes get smaller, the fill factor gets worse. BSI provides the most direct path for light to travel into the pixel, avoiding light blockage by the metal interconnect and dielectric layers on the top-side of the sensor die (see figure below; source:OmniVision)).

The improved low-light sensitivity should  be especially popular in cell phones.

OmniVision and TSMC developed their BSI CMOS sensor technology together and now show a pixel roadmap down to 0.9 micron pixels. OmniVision said that they are  ready to start sampling an 8-Megapixel product using the new BSI-based sensor design called OmniBSI.

Sony

On the heels of the OmniVision announcement , Sony made a similar BSI technology announcement. Sony said it is likely to start applying a BSI technology on their CMOS sensors for 5-Mpixel camcorders or digital cameras with 1.75μm CMOS pixel technology. Sony highlighted the new sensor's superior S/N ratio to its existing 1.75μm-pitch front-illuminated product.

A Comparison of the Sony and OmniVision product announcements follows.

One can expect initial sales to the digital camera market where low light capability has significant value and then, as cost reduction occurs, application in the consumer markets  like cell phones. 

ST Micro

ST Micro working with CEA Leti and Tracit Technologies have also demonstrated the feasibility of manufacturing 3-megapixel 1.45 um CMOS image sensors using BSI technology. They claim to be obtaining a quantum efficiency (QE) (QE = the percentage of photons that are converted into electrons) of >60%.

Choosing the appropriate SOI layer thickness is reportedly important.  A thicker SOI layer increases QE, but it also increases crosstalk [the longer the photo-generated electrons have to travel, the greater the chance that they’ll diffuse into neighboring pixels, thereby increasing electrical crosstalk] . Also essential is control of the dark current [essentially leakage current that flows even when the device is not operating ]. Dark current is linked to crystalline defects in the silicon. It can deteriorate image quality badly. It is a challenge to both FSI and BSI CMOS image sensors.. The quality of the wafer-bonding interface, is critical to diminishing dark current.

 
Their technology is based on SOI, wafer bonding and thinning technologies. In the ST Micro BSI scheme, after the final metal layers are created, a passivation layer and subsequent oxide wafer-bonding layer (WBL) are deposited. The WBL is planarized and a support wafer is bonded to the processed wafer, the CIS wafer is then thinned.

Reported ST Micro Process flow:

• SOI wafer
• CMOS process
• Wafer bonding layer (WBL) deposit and planarize
• Wafer bonding
• Thinning
• Anti-reflective coating (ARC)
• Pad opening
• Color filters and micro-lens attached

Kodak,  Aptina (Micron) and MagnaChip are also working on BSI technology. MagnaChip has shown new mobile phone camera sensor technology with backside illumination.

OmniVision has acknowledged that backside illumination concepts have been studied for over 20 years but feel that they are “…the first to take it to mass production”.
 
A quick google of the patent landscape turned up USP 6429036 "Backside illumination of CMOS image sensor" (Micron) ; USP 5244817 "Method of making backside illuminated image sensors" (Kodak) ; USP Appl 2007/ 0152250 "CMOS image sensor with backside illumination ....." (MagnaChip);  USP Appl 2008/0044984 "Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors." (TSMC); USP 6168965 "Method for Makeing Backside Illuminated Imag Sensor" (Tower Semi); USP APPL 2007/0052050 "Backside thinned image sensor with integrated lens stack" (IMEC) . Exactly who has the strongest patent position ?? I will leave for attorneys to figure out.

Sarnoff

Sarnoff ( the old east coast  RCA Laboratories now a subsidiary of SRI International), have also announced entry into the CIS technology arena. At this years Semicon West a few weeks ago they introduced Ultra-Sense™, a thinning technology that they have developed for high-performance, SOI based, back-illuminated image sensors.

After processes are completed on the frontside of the CIS wafer, the wafer backside is thinned. They indicate that their backside thinning process using SOI wafers gives better control of the thinning process which improves pixel quality , lowers cost and improves the yield. Their business model appears to be  licensing and manufacturing partnerships.

….In keeping with my 3D IC theme of evolution not revolution it is easy to see that such backside illuminated image sensors are now set up for chip stacking with TSV as described in roadmaps such as Zycube/Oki [discussed previously in Perspectives From the Leading Edge , “3D practitioners assemble at Ft McDowell” 3/23/2008 ] I would guess that this is the “high end sensor + dsp” on their roadmap which appears ~ 2010.

For those of you wondering what size market this is - Techno Systems Research ( Japan) has estimated the 2008 total market for CMOS modules to be around 600MM units.

For all the latest on 3D IC integration technology stay linked to Perspectives From the Leading Edge........