Philip Garrou

More 3D Integration at ECTC 2008
June 28, 2008

Replisaurus Update

Before I update on recent presentations at the Electronic Component Technology Conference (ECTC) I wanted to congratulate Replisaurus [ see Perspectives From the Leading Edge "Electrochemical Pattern Replication or ECPR for short" 1/06/2008 ] on their acquisition of S.E.T. [Smart Equipment Technology, the former device bonder division of SUSS MicroTec] to establish production for its high-volume manufacturing tools for their ElectroChemical Pattern Replication (ECPR™) technology. S.E.T. will be a wholly owned subsidiary of Replisaurus. I’m sure we’ll be hearing more about this exciting technology in the future.

James Lu – IEEE Sustained Technical Achievement Award

Congratulations go out to James Lu, RPI, for winning the IEEE CPMT Sustained Technical Achievement Award for his many years of work in 3D Integration. James has helped build the platform upon which we are all now working.

Daniel Donabedian – Welcome on board

Dan Donabedian has taken the reigns as CEO at Ziptronics. Dan previously worked at Elpida. We expect to see some significant announcements from Ziptronics...soon.

ECTC Orlando FL

3D Integration is taking more and more sessions at the Electronic Component Technology Conference. A lot of these papers continue to be about using Si substrates with TSV serving as substrates for SiP. .....Think Si BGA substrates or more properly MCM-D thin film interconnect platforms from a decade ago with TSV through holes. Mind you, I have nothing against MCM-D (in fact Iwona Turlik and I edited McGraw Hill’s Multichip Module Handbook in 1998) but I learned my lessons a decade ago working with startups n-Chip, MMS and Polycon concerning the manufacturing costs of Si based packaging solutions. Anyway….. until I see some clear, convincing economics on such technology I will consider it an expensive niche and will treat it as such in this blog.

RPI

The afore mentioned James Lu and his RPI team presented further details on their Cu/BCB bonding scheme. A lot of their process work several years ago involved a vias last process where wafers were F2F glued together with BCB, the top wafer thinned and vias created down to the pads on wafer 1. This latest technology is more like the Ziptronix process where dielectric bonding occurs with a coplanar copper interconnect structure. In this case the dielectric is not SiO2, it is BCB, so the bonding interfaces are BCB-BCB & Cu-Cu. A typical bonding protocol is 250 C for 60 minutes followed by 350 C for 60 min., both under 10kN of bonding force. So I’m not getting real throughput advantages here, but I do not require underfill to fill in the gaps created in some Cu-Cu bonding processes either. I direct you to the paper for a lot of detail on the interfaces themselves.

IMEC

Eric Beyne and the 3D Integration group at IMEC published some new information on Au/In transient liquid phase (TLP) bonding [ what I and others have been loosely calling "eutectic bonding"] and the use of Parylene for TSV insulation.

The examination of InAu “TLP” bonding was driven by the desire to lower the bonding temperature in devices like memory and sensors, two of the earliest expected 3D integration applications. So their bonding stack was Cu/Au to Cu/Au/Ti/In where 20 nm of Ti was used to prevent In interdiffusion at RT. In the final metallurgical bond all the In is transformed to mainly AuIn2 which is stable up to 450 C (similar to the Cu/Sn scenario) . A minimum In thickness of 0.5 um was necessary to form the bond. 60 um bumps had a shear strength of 1.2 GPa.

The examination of parylene is driven by exactly the same requirements, i.e. lower and lower processing temperature requirements. Deposition seems very conformal in 50 x 100 um vias and patterning and etching in backside vias of these dimensions were possible. I personally still need to see more data on the mechanical and oxidative reliability of using Parylene in such applications.

CEA-Leti

Another long time player in the 3D Integration technology, Leti, presented work on low temp, backside, vias last technology for CMOS Image sensors.

Adhesive bonding to the glass cover layer is done at 110 C for 1 hr. The Si was then thinned down to 70 um and the vias were Bosch etched at 7 um /min. This resulted in maximum scalloping of 0.6 um. SiO2 insulation was deposited PECVD with SiH4/N2 at 150 C. The deposition rate was ca. 250 nm /min. The deposition conformality (measured by thickness on top vs thickness on inside/ bottom of via was 12-18 %. They noted that they are working to improve these results. The vias are electroplated after sputtered Ti/Cu barrier/seed.

IBM

The most interesting of the several IBM papers that were presented were the Steven Wright paper on W Via Testing for High Current Applications and the Sakuma-san paper on die to wafer stacking and bonding.

In the former, Wright tested the reliability of W filled vias under high current stress. The annular vias had a diameter of 77 um. The results indicated that rhte limitations on power distribution with this technology are associated with the solder bumps used as interconnect, not the W filled TSV.

In the latter, Sakuma showed that multiple 70 um thick die could be assembled in stacks on top of a wafer using a single bonding step. This is shown schematically in the fig below where die cavity technology is used for high throughput, high precision automatic positioning.



For the latest updates on 3D IC Integration stay linked to Perspectives From the Leading Edge........

Posted by Philip Garrou on June 28, 2008 | Comments (1)