Philip Garrou

NXP Proposes Passive Integration in 3D IC Stacks
April 13, 2008

Finishing up on my coverage of the 3D Integration technology from last months IMAPS Device Packaging Conference in AZ........

NXP Passive Integration Devices to contain TSV

Yannou from NXP (the Philips semiconductor spinout) gave a very nice presentation on their integrated passive technology which they call PICS (passive integration and connecting substrate). We are not talking about Imbedded passives which are passives buried in PWB layers, but rather thin film components similar to what ST Micro has been manufacturing for several years (and they call IPADs).

Their capacitors are made by the same deep trench cap technology that I have been pointing to as the natural evolution of TSV from the major fabs. PICS 1, for Rf and digital applications, reportedly gives them decoupling caps up to 80 nf/mm sq; Rf caps up to 100 pF and resistors up to 100 KW. Versus the same circuits built on state-of-the-art SMT laminate, they are seeing 10X size reductions !

Their next generation “PICS with vias” makes use of TSV in the Si / thin film substrate to mount micro controllers on top and Rf actives underneath the BGA like silicon structures. Below compare the NEC 3D “SMAFTI” structure to that being proposed / prototyped by NXP.

NXP PICS with active devices and TSV

NEC “SMAFTI”

Datacon C2W Bonding

Kostner from Datacon presented details on their chip to wafer (chip to wafer) bonding technology. Datacon was involved in the original SOLID process developed by IZM-Munich and Infineon. They have now explained in more detail how they do temporary face to face bonding using the chemical “bibenzyl “. After all the chips have been placed, the wafer stack is moved to a wafer bonder for the time / temperature / pressure needed to form the Cu/Sn eutectic bond.

Alcatel DRIE for TSV

Puech, CTO of Alcatel micromachining Systems, presented their latest work on the DRIE process.

There still appears to be a lot of confusion out there on via aspect ratios. Evidently “customers” are asking for a wide variety of via sizes. We have heard this before from Semitool at the 3D meeting in Whitefish last fall. I think the best way to examine the validity of these requests is with the applications figure below (modified from CEA Leti). As we go from left to right the wafers / die are expected to get thinner i.e for image sensors the wafers are in the 50 – 100 um range; for memory stacks the wafers are already at 50 um and going down and for memory on logic and reconfiguration / heterogeneous integration we expect sub 20 um Si layers. Thus I just don’t see anything out there (significant volume) that will be 100:1 aspect ratios, probably nothing > 10-20:1. If someone sees it differently please comment !

Of more interest to me were his remarks on the low temp PECVD of SiO2.

Alcatel claims they can deposit a 2 um thick oxide layer at a rate of 500 nm /min from SiH4/O2 at 180 C. Such materials have a breakdown voltage of 7.5 MV/cm !

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Posted by Philip Garrou on April 13, 2008 | Comments (0)