Philip Garrou

Intel 45 nm Processor Technology for Mobile Products
July 16, 2008

Those of you that keep an eye on the Intel Technology Journal have probably seen the write up on their 45 nm Processor Technology. For those that didn’t , I’ll summarize some of the key points here.

The 45 nm process incorporates high-K+metal gate (HiK+MG) transistors for the first time along with third generation strained silicon, nine copper interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. The electrical performance of these products were covered in an IEDM paper last year [ref].

[ref] K. Mistry et al., “A 45nm logic technology with high K+Metal gate transistors, Strained Silicon, 9 Cu Interconnect layers, 193nm dry patterning and 100% Pb-free packaging.” IEDM Technical Digest, 2007, pp. 247–250

The structure of the flip chip BGA package is shown in the figure below.

The 100% Pb-free architecture was achieved in a phased approach. Cu bumps were incorporated as part of the 65nm process technology in place of the more compliant high Pb-bumps on the silicon die. This was followed by tin-silver-copper (SAC) solder in place of eutectic Pb-Sn, as part of the 45nm technology.

Based on over five years of research experience on Pb-free materials, Intel selected Sn-Ag-Cu solder metallurgy as the flip-chip die attachment material. They found that Sn-Ag-Cu solders have better wettability to metal pads, leading to reduced solder voiding and reduced solder joint open yield loss. They also possess increased solder joint strength due to the suppression of under-bump nickel barrier layer diffusion and intermetallic growth.

Both the Cu-bumps and the SAC solder are much stiffer than their leaded counterparts and impart significantly higher thermomechanical stress on the mechanically-weak, low-K materials on the silicon die. The use of a higher number of low-k-based metal layers in the 45nm products for improved interconnect performance further exacerbates the stress-management challenge. Assembly challenges included ILD cracking and occasional solder joint interfacial delamination. These challenges were resolved by “… an optimization of far backend architecture, design, materials, and processes in both fab and assembly”.

The change to lead-free (Pb-free) solder alloys also necessitated the development of alternate flux materials to clean off the more tenacious tin oxides from the solder surface. The new flux material had to be stable at high process temperatures and show strong adhesion between the underfill, the bump metallurgy, and the die passivation.

As a side benefit, Intel found that the Pb free technology provides significantly better electromigration performance and power distribution performance than typical Pb based joints , as shown below.

In order to meet the size requirements of ultra mobile devices, the physical size of the 45nm packaging technology had to scale down.

Overall package height in mobile devices need to be less than 1mm. In order to achieve significant package height reduction Intel developed a high volume manufacturing process for wafer thinning 12-inch, high-density bumped wafers down to 75um. In the case of the organic substrate, a standard build-up core of ~800um is used for typical packages. By wafer thinning and reducing the build-up core thickness, Intel developed the capability to produce flip-chip packages with heights that are 33% less than standard packages.

Scaling down the size of these packages requires the board-level interconnect to scale as well. In the case of the 45 nm processor technology, the ball pitch scaled down to 0.6mm from what was previously 0.8 to 1.27mm pitch.

Mechanically drilled vias do not scale well and limit the package ball pitch to approximately 0.8mm. Thus, for 45 nm interconnect Intel was required to use High Density Interconnect (HDI) motherboards shown in the Fig below. The laser drilled microvias are significantly smaller than the mechanically drilled vias and allow the signals to break out from the package.

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Posted by Philip Garrou on July 16, 2008 | Comments (1)