Philip Garrou

A Rose by any other name is not 3D IC Integration
November 20, 2007

First of all, thanks for visiting this blog. Evidently 2750 of you dropped by to see what was happening “on the leading edge” in October. I will try to keep the information here fresh, up to date and relevant.

Just got back from a reunion I have every year with the kids I grew up with in Hells Kitchen. As you get older you will find that your oldest friends become very dear friends. Anyway if you need a change of pace from all this heavy 3D technology, and have any interest in what things were like in downtown Manhattan in the early 1960’s try our web page at www.lasallejhs17.com, you will be entertained – I promise.

3D integration, like my old neighborhood friends 40 years ago, is in the process of growing up and I am seeing the natural turf fights that go on in any hot new technology. Societies are rolling up their sleeves to battle it out for who gets the biggest piece of the 3D integration pie and everyone who wants to be in on the leading edge has jumped into the fray and become an expert on 3D. Unfortunately “3D” may be replacing “nano technology” as the buzz word of the week.

People are beginning to define 3D as whatever it is that they happen to be doing. This Clintonian effort to spin 3D into their desired activity, will, in the end, only cause confusion in our community.

For instance, in the Aug/Sept issue of Chip Scale Review Belgacem Haba of Tessera presented a very nice review of the evolution of “3D stacking”. By my way of thinking 3D stacking whether using wire bonding or edge connections (Irvine Sensors or Vertical Circuits) is 3D Packaging, to be sure, but not 3D IC integration. As I’ve stated in a number of places the easiest way to spot 3D IC integration is to look for (3) things: (1) thinning; (2) bonding; (3) through silicon (or other semiconductor) vias. Some of the packaging folks from IBM are now saying that mounting a chip on a silicon substrate is “3D Integration”. Again, any stacking, by definition is 3D , but if their definition is true, then mounting a through hole component on a PWB is 3D integration also! Lets keep the definitions realistic guys – 3D IC integration has TSV.

On Nov 15th Advanced Packaging magazine (PennWell) held an EVG sponsored webcast entitled 3D Packaging – which way to go. I think it is still available on their web site if you care to spend an hour listening to it.

When your done you will not, as promised, understand “which way to go” but you will have picked up some interesting information on 3D.

Jerry Bautista describes the reasons of Intel moving to “terascale processing “ and details the bandwidth reasons we have mentioned before for moving to 3D IC integration. A nice cartoon of the 80 core processor on memory 3D stack is shown below.

Jean-Christophe Eloy of Yole consultants points out the very logical sequence for 3D commercialization: 2008 – form factor driven ( CMOS image sensors [CIS] & flash); 2010 performance driven (DRAM, Rf, memory on processor ; 2012 cost driven for all applications. Although we could argue that their overall timing is aggressive, this sequence is logical and makes sense (I like it when things make sense).

By 2010 they project that no less than 9 memory suppliers will be in commercial production with 3D IC integration (The Perspectives from the leading Edge definition meaning containing TSV) This is reproduced below.

Paul Linder of EVG gave a presentation detailing EVG presence in EMC-3D consortium (see my Aug 26th blog entitled 3D Equipment & Materials Vendors Consortium) and describing their 3D applicable tools such as wafer bonders, aligners, resist coaters, temporary bond / debond tools ect. An especially nice slide of the bonding process for CIS (CMOS image sensors) is shown which I’ve included below. Note they are recommending that a low cost route to via insulation is by spray coating with their “nano spray coater” They claim they can handle 1:4 aspect ratios and have done 20 micron vias. This is an interesting option and merits further consideration. The issue will be whether the recommended sprayable materials such as BCB will be able to sustain subsequent processing conditions.

Stay linked for more “Perspectives from the Leading Edge”……………………….

Posted by Philip Garrou on November 20, 2007 | Comments (0)