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3D discussions in the valley... continued
November 4, 2007
Continuing with coverage on the RTI "3D Architecture for Semiconductor Integration & Pkging meeting that occurred Oct 22-24th...........................
Ted Vucurevich, CTO of Cadence indicated that they would be developing 3D tool sets “...once it is clear that the market is going this way” I’m not sure how clear it has to get for them ?? He added that he thinks memory will be the driver, but he also said on one of his slides that TSMC had “announced capability”. To the best of my knowledge TSMC has NOT announced capability although they are actively working in the area.
Yole, a market analysis group from Europe, who has focused mainly on MEMS in the past, has given several presentations of the status of the 3D market in the last year. Their most recent numbers in SF included 2010 equipment and materials markets of $800MM and $600MM respectively; 5MM wafers being done in 3D in 2012 and 2012 breakouts of 63% of the image sensor market, 20% of the DRAM market and 30% of the flash market. My opinion is that these are VERY aggressive numbers from where we are starting now (at zero) as 2008 is about to begin.
Jan Vardaman of TechSearch presented a more restrained picture ( note I work with Jan in the 3D area – the full disclosure thing !) . Jan projects we will not see the first 1MM 3D wafer / year, year till > 2010.
A panel session comprised of Tezzaron, Rambus, Toshiba, Intel and Samsung were to address the theme “Is 3D memory with TSV ready for prime time”. There was some “hemming and hawing “ and some “tap dancing” but the highlights consisted of: (1) Toshiba will begin CMOS imaging chip production in Jan 2008 (check back 2 blogs for details) with TSV ; (2) we need some standardization on the memory I/O; (3) I/O must be redesigned to have a mixed memory stack; (4) there are currently no DRAM solutions after DDR4 ; (5) we’ll probably see performance driven 3D after 2008 and cost driven 3D after 2011.
On Day 2 Amkor went public in a presentation by Lee Smith with their roadmap to TSV 3D. Most of this work is occurring at their RTP NC site now that it has become a R&D facility and bumping and WLP production has been moved to Taiwan. Amkor 3D development consists of internal development at the aforementioned RTP NC site; membership in the IMEC 3D consortium and membership in a Korean 3D consortium.
As shown in the slide below they predict that the migration to TSV stacks will occur when the cost adder is small enough to justify the size and performance benefits (see figure below). They feel they will be ready for Rf, memory + memory and memory + logic TSV stacking in the 2008 – 2010 timeframe.
With this formal announcement by Amkor we have now seen ASE, STATSChipPac and Amkor all make announcements in 2007 that they are getting ready to support the assembly of 3D integration technology.
Kada-san from ASET (Assoc of Super Advanced Electronics Technologies) in Japan indicated that the ASET group was ready for round 2 of 3D integration where they will concentrate their studies on: (1) design; (2) test ; (3) head-to-head evaluation of the technologies that have been developed thus far. Very good choices in my opinion.
...........Stay linked to Perspectives from the Leading Edge for all the latest 3D integration information........................................
Posted by Philip Garrou on November 4, 2007 | Comments (0)
