Philip Garrou

3D Equipment & Materials Vendors Consortium
August 26, 2007

Last fall equipment providers, materials companies and packaging Institutes joined together to form an international consortium EMC-3D. Their stated  goal is to develop the 3D market infrastructure by demonstrating a cost-effective, manufacturable, stackable TSV interconnection technology. 

http://www.emc3d.org/

Year by Year goals include:

Year 1 - Demonstrate integration (or stackability) of via-first TSV technology on 200mm wafers with members’ equipment and process technologies with CoO≈400-500$ / wafer.

Year 2 - Demonstrate integration and reliability of TSV technology(via-first or via-last depending upon technology trends) on 200mm wafers with members’ equipment and process technologies with CoO ≤300usd per wafer.

Year 3 - Demonstrate seamless integration and reliability of TSV technology (via-first or via-last depending upon technology trends)on 300mm wafers with members process and equipment technologies with CoO of < 200$ / wafer.

 Equipment companies initiating the consortium as founding members are:

• Alcatel Micro Machining Systems (Annecy, France) for via etch
• XSiL (Dublin, Ireland) for laser drill and dicing
• Semitool (Kalispell, Mont.) for wet processes (via plating, RDL plating and wafer thinning)
• EV Group (Schärding, Austria) for wafer/die alignment and stacking

Associate Institutes include:

• Fraunhofer IZM,  Germany
• CEA LETI, Grenoble, France)
• SAIT (Samsung Advanced Institute of Technology), Seoul, Korea
• KAIST (Korea Advanced Institute of Science and Technology), Daejeon, Korea

Material supplier members include:

• Rohm and Haas Electronic Materials, Freeport, N.Y.)
• Enthone Inc. West Haven, Conn.
• AZ Electronic Materials, Somerville, N.J.
• Honeywell, Spokane, Wash. 
• Brewer Science – Rollo MO

Major processes being integrated into the EMC-3D program are:

• Via DRIE etch and laser drill (5 -30 µm on 200 and 300 mm wafers)
• Insulator/barrier/seed deposition
• Micro via patterning with RDL capabilities
• High-aspect-ratio copper plating
• Carrier bonding/debonding
• Sequential wafer thinning
• Backside insulator/barrier/seed deposition
• Backside lithography
• Backside contact metal plating
• Chip-to-wafer placement and attach
• Laser dicing

Their stated year 3 COO goal of $200/wafer certainly appears challenging today . To keep things in perspective, however, recall the early days of bumping / wafer level packaging (less then a decade ago) when consortia like SECAP proposed similar challenging COO goals. The prevailing thought back then was that bumping was a high end thin film technology used by the likes of IBM and NEC and would never be a low cost technology for consumer products. However we now, in hindsight, know that the time was right and the technology was right.  Bumping / WLP  is now a basic packaging concept for portable consumer products. 

Will 3D integration follow a similar path ?? Hard to say.  Bumping / WLP really took off once the technology options had been whittled down and the packaging houses in Taiwan and Korea announced they were licensing technology from FCT and/or Unitive and putting significant capacity in place.  It will be more complex in the 3D case since the IC foundries and packaging houses will  have to be much more coordinated and aligned to produce and package 3D chips. 

In this cse keep on the lookout for announcements on imaging chips  and memory suppliers. It's likely they will be the early adopters and their product announcements will be a key to how fast this all proceeds. .........more later

Posted by Philip Garrou on August 26, 2007 | Comments (0)