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3D IC Integration : Evolution or Revolution ?
March 16, 2008
As we get older we begin to understand that most technological advances are made in an evolutionary, not a revolutionary manner. I would further contend that paradigm shifts are only seen in hindsight. When an industry, such as Microelectronics, is faced with technology that requires major changes, the industry is usually resistant, because it is extremely difficult for the in place infrastructure to adjust and accept. Like the turtle, slow but steady progress always ends up winning the race.
When it comes to 3D IC Integration, we are currently involved in part of the larger merger, or blending, of packaging technology with on chip BEOL interconnect technology. I predict that 20 years from now technologists will look back and see this era as the one in which packaging and on chip technology truly became blurred and that 3D IC integration, in hindsight, will be viewed, as the paradigm shift that finally pushed this merger over the edge. But as Dennis Miller would say....”that’s just my opinion, I could be wrong”
For example in past Perspectives From the Leading Edge blogs I have proposed that 3D IC integration will evolve from the following actions : (A) bonded wafers without 3D vias similar to the Infineon / IZM Munich “SOLID” technology; (2) CMOS image sensor devices with backside TSV but no wafer stacking and (C) memory stacks using today’s memory chips and connecting them with TSV through current pad structures. These are the baby steps that will someday lead us to what we all envision - the stacking of repartitioned IC strata which will all include some variation of thinning, bonding and TSV.
Bonding wafer to wafer (W2W) or chip to wafer (C2W) without TSV is sometimes called chip-on-chip (CoC). Wafers or chips are thinned and face to face bonded. The bottom chip is larger and usually has peripheral pads which allow subsequent bonding of this face to face chip sandwich by WB or BGA like structures. To the best of my knowledge, this concept was first proposed and prototyped by Bob Frye and the rest of the the old Bell Labs MCM ( multichip module – today called SiP) research group in the late 1990’s.
At the end of 2005 Sony implemented CoC, bonding DRAM directly to logic for the playstation. One of the reported reasons for the change was that Sony was unable to find any way to make the chip cheaper by scaling from 90nm to 65nm merged DRAM process technology. "A massive capital investment would have been needed to drop the design rule to 65nm....and even if we had single-chipped with DRAM and the logic, each demanding a different manufacturing process, it would have taken a long time to get the yield up." [“Chip-on-Chip Offers Higher Memory Capacity, Speed” Nikkei Electronics Asia, February 2007]. This is a natural evolutionary step....commercialize bonding , then commercialize TSV.
In similar fashion we have described CMOS imager wafer level packaging being put on line by Zycube/Oki ( see Perspectives From the Leading Edge - More commercial TSV Capacity on line, Dec 5th 2007 ), Toshiba (see Perspectives From the Leading Edge – Imaging Chips with TSV announced for commercialization, Oct 27th 2007 ) and most recently ST Microelectronics (see Perspectives From the Leading Edge - ST enters CIS camera market place with 3D TSV technology, March 5th 2008 ). These are simple, one device layer, wafer level packages but these vendors are learning the intricacies of commecializing TSV. I bet that all of them are working on the next generation stacked structures (see below for a confirmation from ST Micro).
Samsung has shown us both NAND and DRAM memory stacks, although never indicating when, or if, they would be put into commercial production. It is interesting that in all of these stacked products they are thinning to an unspectacular 50 microns and putting the TSV right through the pads that are already there (for a cross section see Perspectives from the Leading Edge - …Rumors and Ruminations, Feb 8th 2008). No chip redesign and no thinning to 20 microns or less….YET. My best bet would be that Samsung is tweeking the technology to lower cost before the put such stacks into their phones. Maybe, since they control the memory manufacture and the phone design, they will insert 3D stacked memory into a selected phone and only tell us in hindsight, when it has been successful……It’s been done before with new technology.
Anyway…it is these baby steps that we should be looking for. Like I said.....evolution will lead us to the vision of the future.
More on the ST Micro CMOS Image Sensor packaging announcement
Info from Mike Hundt [ST Micro] indicates that the ST CMOS image sensor products are being done in house in their Crolle FR facility in both 200 and 300 mm formats. They thin down to 70 microns then laminate on the 500 micron glass cover. They are now working to apply this technology to stacked die products where memory would be added to a media processor.....................
This week I will be reporting back from the IMAPS Device Packaging conference in Scottsdale. For the latest on 3D IC Integration stay linked to Perspectives from the Leading Edge
Posted by Philip Garrou on March 16, 2008 | Comments (0)
