Philip Garrou

EVG discusses status of 3D Integration
January 20, 2008

As I’ve mentioned before when it comes to really knowing what’s going on in the microelectronics industry there are only two knowledgable sources –material vendors and equipment vendors.

Earlier this month I was able to interview Steve Dwyer, VP and GM of EVG NA and Thorsten Matthias, Dir of Technology, about their perspectives on the approaching commercialization of 3D IC integration.

Aside from being founding members of the EMC-3D consortium (see past blogs for details), EVG is supplying the following tools to the infant 3D marketplace: Smartview® aligner/bonder for wafer-to-wafer (W2W) technology, nanocoat spray coaters for coating surfaces with topography and they have joint programs with Brewer Science to supply to supply temporary bond / debonding technology and with Datacon to supply chip-to-wafer (C2W) bonding technology.

They have recently increased the F2F alignment accuracy on the Smartview to 0.5 um for 200 mm and are testing the technology for 300 mm. The technology will be available at a “European research Institute” shortly and will be fully released to customers by the end of Q1.

A Nanospray system has been installed for production at a TSV application customer.

The Brewer / EVG bond / debond technology “.. is now in volume production on a 3D product using the Brewer HT-250 adhesive. The first 300 mm production equipment will be shipped in May”. Mathias indicates that new Brewer materials with stability at 300 °C should be available later this year.

Dwyer views the main goal of the EMC-3D consortium as “.. reducing the entry barrier for customers by establishing and qualifying standard process flows which customers can in turn customize to meet their own needs. ...basically eliminating the unknowns for them “ Potential customers are looking for “...someone to deliver a fully qualified process with known production costs”

When asked about the activity at assembly houses Dwyer responded that “...most are well along on studying the various 3D process options but they are still a bit hesitant to commit until the industry leaders narrow things down a bit and give the overall market better direction.”

When asked for his opinion on the market numbers that have been published to date (pre-2008) for materials and equipment use, Dwyer answered that they seemed very aggressive. He agreed with everyone else that CIS (CMOS Image Sensors) would be the first application in production (It is already with recent announcements from Toshiba and Oki – see previous blogs) and then added that he believed that we would see “...DRAM volume next... probably in 2009”. Neither Dwyer or Mathias have seen stacked CIS yet, but added that it was a logical next step which they both expected.

Two of the main integration questions for 3D processing remain vias first (before stacking) vs vias last (after stacking) and choosing bonding technology from the options metal-metal (Cu-Cu or Cu/Sn eutectic) vs oxide bonding vs polymer bonding. Matthias offered the following observations. EVG sees a strong movement towards Cu-Cu bonding despite high temperature ( ca. > 400 °C) and time issues (wafer must be held in the bonding tool for ca. 1 hr to form a reliable bond). They also see some adoption of Si fusion mainly because it allows rapid interface formation at RT and allows for rework before subsequent thermal anneal forms a monolithic SiO2 interface. They do see some hesitancy with fusion bonding which they think this is due to the stringent surface preparation requirements which are difficult for practitioners to achieve unless they are commercial in IC technologies like Dual Damascene. They have seen no commercial adoption of polymer bonding technology to date.

In terms of W2W vs C2W Matthias points out that it all depends on the desired accuracy. “...W2W has a perceived production throughput advantage since all chips on the wafer are aligned at once and it can achieve < 1 um accuracy today.” C2W allows the use of KGD but throughput is much more dependant on required accuracy. For instance, EVG / Datacon technology can place 7 – 10,000 die per hr with 10 um accuracy and then bond them all at once but if 1-2 um accuracy is needed, one could only bond 100-200 die / hr. “

Although current publications show prototype devices from Samsung and Elpida / Oki which appear to be derived from individual chip stacking, Dwyer and Matthias offered a “no comment” and a wink when asked whether logic dictated that they were scaling W2W processes although not showing them publicly.

When asked their opinion about the timing for IC foundries to offer “vias first” technology they responded that they had seen some hesitance on the part of the Asian mega foundries, they believed because of their unfamiliarity with wafer bonding technology which really evolved for the MEMS and packaging segments of the industry.

Hope this has been of interest to you. For all the latest on 3D IC Integration be sure to stay linked to Semi Internationals “Perspectives From the Leading Edge.”

Posted by Philip Garrou on January 20, 2008 | Comments (0)