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3D IC Questions and Answers with the EMC-3D Consortium
October 5, 2008

 

Many of you have seen the recent press release by the EMC-3D consortium that they have reduced the cost of ownership for a 10K wafers-per-month line to less than $190 per wafer. I thought it would be of interest to the readers of PFTLE, to have them expand upon this announcement.

 

For those of you who are not familiar with the composition and goals of this group check out previous blogs [ PFTLE “3D Equipment & Materials Vendors Consortium” 8/26/2007] or the EMC-3D consortium web page.

 

The process that they describe includes “…litho and hard mask for the etch process, DRIE for the via creation, thermal and CVD liner and barrier, wet copper seed, copper electroplate fill, CMP and associated wafer cleans to complete the via. The wafers are then processed using standard CMOS technology and finally passed back to the TSV group for backside processing, including thinning, lithography, copper redistribution, solder bump, dicing and die-to-wafer-placement using temporary adhesive bonding before the final die attach step for a complete process flow.” The process is shown in the figure below.

 

 

They have reported that the EMC-3D cost model identifies the current complete Cost of Ownership to be $189 per wafer for via-first (which they are calling iTSV™ )or vias last, (pTSV™) on 300mm wafers. Their consortium goals for next year are to further reduce these costs to under $145.

 

I recently had the opportunity to correspond with Rozalia Beica, program manager of EMC3D and TSV director at consortium-member Semitool, who I know since her old days at Rohm & Haas. Rozalia has supplied PFTLE with the pie chart below which breaks out the 3D integration cost by unit operation. This offers a very interesting perspective on where the costs are.

 

 

Rozalia was also kind enough to respond to the following questions:

 

PFTLE: My perspective has been that EMC3D has focused a vias last approach. Can you expand on why and comment on how the numbers come out for a vias first pSi filled and/or W filled via process flow vs a vias last flow.

 

Beica: The consortium has always had both the via last and first as an objective, we’ve just prioritized to assure valuable R&D equipment would be utilized well. Technically, both via first and last are doable, the challenge is how we can better balance cost and performance. We took in consideration all the processing options we currently have, their cost and applicability with respect to feature design and integration, and chosen the processes and materials that can provide the most robust and manufacturable integration technology for each approach (via first and last), where was possible, using the less expensive processes currently available.

 

For some of the processes, certain steps will be more or less expensive, depending on the size of the via. Let’s take for example the 5x30µm feature size. Because of the challenges associated with etching processes (need less scalloping for assuring better coverage with barrier/seed insides these small vias) as well as PVD depositions in such high aspect ratios, we have decided to look into this type of features in more detail and develop processes that can overcome these limitations and be, in a cost effective way, successfully integrated.

 

For this and other type of features that have ARs> 4-5:1, the traditional, less expensive, PVD systems cannot provide the uniform and conformal seed coverage on the sidewall required for uniform copper nucleation and superconformal via filling. More advanced PVD systems, such as IMP are required; however, these are significantly more expensive. An alternative method to PVD, which we have been working on for quite some time, is wet seed layer deposition (direct on barrier deposition). Because the CoO numbers for PVD Cu-seed are quite high for such vias, we have selected to use the wet seed for now, although work is also being done to make that step less expensive. The wet seed deposition is currently the preferred option for high AR vias.

In reducing via sizes, the pick and place and die attach, require greater placement and the cost will be higher than pTSV type vias. There is a benefit also, the smaller via allows for faster electroplating and CMP, so the overall cost is quite reasonable.

 

A strong focus of all the members of the consortium continues to be the improvement of each unit process and integration. Today we came along way since this consortium has started. We better understand each process, estimate more accurately the costs, understand the challenges associated with integration of TSV technology, being able to choose and recommend to our customers and the industry the most suitable, robust and cost effective processes.

 

PFTLE: In what instances does the consortium think that D2W is the preferred process over W2W? Any comparisons of D2W vs W2W in terms of cost ?? (at the same assumed yield)

 

Beica: Members like EVG and Datacon are working on both. Although W2W stacking is, in general, considered a more favorable approach because of increased throughput, W2W cost is estimated to be higher than equivalent D2W stacking because of the lost-good-die during W2W bonding…. thus KGD can enable overall higher yields than W2W approach.

 

Also, alignment of the chips and bonding will become more complex and difficult through W2W approach once disparate technologies start to be integrated in heterogeneous packaging and dies of different sizes will have to be stacked. For the cost model within the consortium we’re focused on D2W as that seems to be the more common option today.

 

PFTLE: Many feel that throughput on the bonder (for Cu to Cu bonding ) is the biggest cost factor. Your pie chart seems to agree with this. Is the consortium focused on doing anything to lower the cost of this operation ?

 

Beica: That is true. …now that the cost is clearly identified, each consortium member has internal roadmaps to aggressively attack the cost, we expect the accuracy and speed to improve greatly in the near future and [bonding] cost to significantly drop.

 

PFTLE: Can your share the cost difference between a DRIE process and a Laser process holding everything else constant.

 

Beica: Not at this time.

 

PFTLE: EMC-3D has made it clear that there is no "license" that is available from the group. Is there a full process that is turned over to a "customer" or does the customer have to put the parts together from the individual members ?

 

Beica: The consortium was created to address the technical and cost issues of creating 3D interconnects using TSV technology. We have several major equipment manufactures and material companies that work together with leading research groups to address the issues of cost-effective manufacturing and integration. The individual process steps are ‘licensed’ with the equipment, but we are not planning to coordinate an overall 3D license. The unit processes are available to any interested party from each member individually. One of the beauties of EMC3D is that it is an “open” consortium. Customers are able to pick or omit any of the members tools/materials, with no obligation. This generates a healthy competition. For prototype development, the customers can work directly with any of the EMC3D members or have the consortium coordinate the work within its members. We are working very closely together within consortium, using our own test design for solving all the integration issues, and also in supporting demos and other requests for our customers.

 

PFTLE: Are the tool vendors filing IP on their operations ? Will the customers need to license any IP to engage in the EMC3D "process flow"?

 

Beica: The main objective of EMC3D consortium is to develop a cost effective and manufacturable process (unit processes and integration), equipment and materials that can be fully adoptable by the industry. We use process flows within consortium, however they are not for licensing, are just examples of the process flow, equipment and materials we use for demonstrating chip integration using consortium members technologies. As I mentioned above, the IP is built into the equipment and materials with respect to each company and customer relationship, however, with respect to process flow, there is no IP.

 

PFTLE: Can you name specific companies that are engaged in scaleup with EMC-3D ?

 

Beica: Unfortunately, I can’t reveal any….. this is confidential information.

 

PFTLE: Any comments on the AR issue ? Why is anyone looking at > 50 um dia vias or > 5 AR ??? What are these applications aside from Si BGAs (i.e. Si SIP substrates with TSV) ?? I do not see the need for AR > 5 until we need ~ 2 um or smaller vias in 10-20 um Si and my opinion is that for the vast majority of the market space that will not be for some time.

 

Beica: We are seeing a wide range of requests from customers, vias from 2µm to 90 -100µm with depths of 10µm to 300µm and even deeper, and a large range of aspect ratios, higher than 5 and even higher than 10:1. Most of them in the range of 5-10 AR.

 

The vias larger than 50µm are usually applied for CMOS applications, however, Cu lining is good enough for this, so no COO issues here, reason for which they are already in production. For all the other applications we see feature sizes with lower diameters.

From pure COO stand you are right, however many companies are currently taking advantage of the large free area around the peripheral of the chip. As design becomes more common, internal die vias will be much more common; the real estate there is more critical so the via sizes will have to be decreased.

 

Another reason for using larger vias (especially in case of the packaging houses who are looking more at via-last approach and using thicker wafers), is due to their access to less expensive, older technology PVDs for deposition of barrier and seed. They had to choose larger diameters to stay below the critical ARs of traditional PVDs. However, with new, less expensive alternatives that can be applied to more aggressive ARs, as well as higher performance and more cost effective PVD systems that will hopefully become available to the industry in the near future, I believe more and more companies will reduce their via sizes. Another advantage of having smaller vias is, besides, the ability to manufacturing higher density interconnects, the significant decrease in processing times for metallization step (as I mentioned above as well). Reducing the processing times will result in increased throughput, thus lowering the processing costs associated with metallization. We are already seeing a trend in the industry of going towards smaller features.”

 

PFTLE: Does EMC 3D have any position on application timing. My market timing projections are shown below, i.e. CIS followed by DRAM starting around 2010 ( for high end applications) followed by memory on logic (once the vias first memory is available) followed by the other applications which we loosely call “heterogeneous integration” . I do not see FLASH happening until the in place infrastructure has driven cost down, since flash is so price sensitive. My read is that will be 2012+ Does EMCD have a similar roadmap which agrees or disagrees with this.

 

 

Beica: In general, we agree with your sequence.

 

PFTLE: Yole has been much more aggressive in their 3D IC market numbers than TechSearch especially in the timing and volume for DRAM and FLASH. Does the consortium have customer data that backs one or the other ??

 

Beica: The consortium does not have a position on anyone’s marketing numbers. We believe that both organizations are competent marketing organizations.

 

PFTLE: If the readers have any further questions for Rozalia they can leave them below.

 

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Posted by Philip Garrou on October 5, 2008 | Comments (2)