Philip Garrou

COSMOS
April 19, 2008

By now, if you’re a reader of this blog, you know that I am preaching that 3D IC intregration will happen in an evolutionary not revolutionary fashion (which is how all things have happened in microelectronics over the past 50 years.

We have mentioned several times that 3D process flows have three unit operations in common: (a) TSV formation; (b) thinning and (3) bonding. Since thinning has been optimized in numerous other applications, the infrastructure is currently focused on introducing TSVs and bonding into mainstream production. Bonding technology without TSVs has been introduced by Infineon and Sony and TSVs without bonding are being commercialized by the various image sensor fabricators that we have been discussing over the last few months.

You should also be aware that most practitioners are now in agreement that the applications space for 3D will likely see commercialization in the following order: (a) image sensors – where the second generation products will be stacked (bonded) with DSPs; (b) some form of memory stacking with TSVs (probably DRAM before FLASH); (c) memory bonding to processors and other logic chips (in order to address latency issues in applications like multicore processors) and (d) heterogeneous integration - where stacking will allow the integration of otherwise incompatible technologies (powerpoint “dream” stacks are typically shown containing microprocessors, sensors, memory and thin film batteries, etc.... ) .

While we have discussed the first 3 categories we really have not yet touched on the fourth. There actually is a major program ongoing in heterogeneous Integration and it is the DARPA program COSMOS.

When you hear COSMOS your mind probably flashes to the deck of the Starship Enterprise where Scotty is begging Captain Kirk ...”I need more time Captain...I need more time"...But, in this case we are using COSMOS as an acronym i.e. Compound Semiconductor Materials on Silicon. The logic for this Mark Rosker MTO program goes something like this... “The development of compound semiconductor (CS) electronics has been motivated by their unique materials properties relative to those of silicon. However, the advantages of the incumbency of Si integrated circuits (ICs), the enormous investment that has been made in such technologies, the decades of progress that has been made in VLSI integration and device scaling, and the dramatic cost reductions for Si ICs have combined to limit the market penetration of CS technologies. Given these trends, it has been increasingly clear that the future of CS electronics depends not on supplanting silicon, but rather on heterogeneous integration of CS with silicon.”

The objective of the COSMOS program, which started ~ 12 months ago is to develop a viable process for the heterogeneous integration of CS devices with standard Si CMOS and to establish that this integration enables superior performance in specific mixed-signal circuit demonstrators. The program focuses on: placement of CS devices, heterogeneous integration and dense heterogeneous interconnects. Participants have been asked to place CS and Si-based transistors in ≤ 5μm minimum proximity, with ≤ 5μm minimum pitch of the heterogeneous interconnect vias and yield of ≥ 99.99% of the heterogeneous interconnects.

The COSMOS program is being conducted in three phases. Phase I will develop and demonstrate a viable process technology to integrate CS and Si CMOS transistors on a very short size-scale within a small circuit (transistor-scale integration technology. Phase II will focus on yield enhancement & circuit integration. In Phase III the COSMOS process will fabricate a heterogeneously-integrated 16-bit analog-to-digital converter (ADC) which will support 98 dBc of SFDR across a 500-MHz bandwidth.

Three teams, led respectively by HRL (Hughes), Raytheon and Northrop Grumman (West Coast) have won contracts and are actively developing their versions of 3D IC integration technology. I was at their program review a few weeks ago but really cannot go into the details of their processes because such info is restricted. At this point, I can say that there has been significant progress on all three routes and heterogeneous integration looks viable for the future.

......for all the latest on 3D IC integration stay linked to “Perspectives from the Leading Edge”

Posted by Philip Garrou on April 19, 2008 | Comments (0)