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It Depends on What the Meaning of Is, Is
September 16, 2008
We all remember the classic line of slick Willie Clinton when confronted by grand jury interrogation about his extramarital activity in the oval office. It went something like “…well it all depends on what the meaning of is, is” That was the first thing I thought of when I saw the 3D IC headline from EE Times on Aug 11th 2008 which read “First 3-D ICs debut” and then saw the Semiconductor International headline “S KOREA DEVELOPS WORLD'S FIRST 3D CHIP MANUFACTURING PROCESS”. Well….actually truth be told the very first thing to flash through the old synapses was “…how did someone get into production without my knowing it ??” ….but I quickly blew that thought off because that was impossible (just joking). So we’re back to what did that headline mean ?? Lets take a bit closer look at what is going on.
BeSang spun out of the Stanford Nano fabrication research facility and their work on 3-D ICs and multibit vertical flash memory technology. The technology is based on a surrounded gate transistor (SGT) structure, where the source, gate and drain are stacked. The vertical memory cells are then placed on top of a CMOS memory control logic wafer, effectively reducing the size of the die and reportedly providing significantly more die per wafer. This is shown pictorially in the figure below.
BeSang argues that “..current planar 2D chips that contain memory must surround their memory arrays with logic circuitry to address bits and to perform logic functions. Placing memory and logic alongside each other forces the use of long interconnection lines between the two.” So far this all sounds a lot like the arguments for 3D IC, i.e. separate and optimize the processes on separate wafers and then join them together.
The process flow, which BeSang has made public in several conferences in the past few years is shown in the figure below. BeSang creates logic circuitry, using a standard CMOS process on one wafer. A doped wafer is then bonded to the CMOS wafer and the excess Si cleaved off ( I imagine in something like a “smart cut™” process). The doped Si layers that remain behind are etched and processed into the memory cells which are then connected with standard vias to the logic circuits in the wafers below, enabling very short interconnection lines between them. The memory cell process is unique in that it reportedly never exceeds 400 °C.
The process has reportedly been exercised on 180 nm CMOS processes at the National Nanofab Center (NNFC) in Daejeon, Korea and the Stanford Nanofab (SNF) in Palo Alto, CA on 200 mm wafers. A test vehicle has reportedly been built which contains 128 million vertically oriented devices.
BeSang claims their single-chip 3D IC technology will produce four times more die per wafer because the memory cells placed on top of a memory control logic wafer, make the effective NOR flash memory cell size “0.5F2” when the multi-bit vertical flash memory array is implemented.
BeSang Process Flow
The Companies web page indicates that it will enter the semiconductor image sensor ( creating diodes instead of memory cells) and memory businesses in both the stand-alone and embedded memory markets.
Lets look more closely at BeSang’s claim ( we all know BeSang wrote the news releases just like every other company does) that (a) this is a 3D IC process and (b) this is the “first 3D IC manufacturing process”. because it all depends on what the meaning of is is …...
Some IC purists contend that real 3D is only accomplished by incremental processing layer by layer on a single wafer. These are the folks who try to grow layers of crystalline Si on already fabricated device layers. This, in theory, would allow the exact same design rules to be applied anywhere in a 3D device. The 3D IC wafer stacking (with TSV) that I have been describing in PFTLE for over a year now, to the purists, is called “2.5D”, because of the "limit" on the vertical pitch of interconnect which is set by the alignment requirements during bonding of two separate wafers/die. So what is the BeSang Technology ?? Well I have consistently stated that 3D IC integration involves the following enabling technologies: (1) TSV formation, (2) thinning and (3) die or wafer bonding. So indeed BeSang is a 3D IC integration technology because it does thinning (albeit by something like “Smartcut™” ), certainly bonds two pieces of Si together ( I have yet to confirm that this is by oxide bonding) and certainly bonds the upper layer to the lower layer using vias that go through the top layer to the bottom wafer (per their own cross section drawings).
When it comes to whether BeSang technology resulted in the “...first 3D ICs” there, I think you might get a lot of argument from the likes of Samsung, Elpida, Intel, IBM, Tezzaron and many other companies and institutes who have built actual functioning 3D IC chips ( not just test vehicles) and described their full processes before August 2008. In actuality NONE of them are fully commercial. As we have stated before, this whole 3D process is incremental. F2F bonding (without TSV) is commercial in many products and TSV are now commercial in many products like CIS and power amps (without stacking) but no one has yet “debuted the first 3D IC” . So as far as PFTLE is concerned that honor is still available for the taking !
While researching this area, I contacted some of my hard core IC friends (academic and industrial) to see what they made of this technology and got some interesting responses, the most controversial of which, I have listed below. I do not defend these responses, I only throw them out there for you to ponder and comment on, if you wish, for they certainly are “perspectives from the leading edge”.
1. “I would also beg to differ with their claim as to this being this first 3D-IC device. Manufacturers of large slow SRAMs have built pfet transistors on top of nfet transistors in the silicon substrate for more than a decade. The pfets are really poor transistors, but they work and people have built 10s of millions of these devices. Also, Samsung demonstrated an SRAM made in 3 layers about 2 years ago….”
2. “To my knowledge they have only produced a flash memory device. They could possibly build DRAM, but given the surface topology this would be at least very difficult, and the size would be larger than 2D solutions.”
2. “To get a reasonable density with the vertical transistors, they have shorted all of the gates together. This works for their flash device, but nothing else. If you don't short the gates, the vertical transistors are bigger than 2D devices.”
3. ”The transistors must all have the same gate length. I don't know of any real circuits that can be built out of one transistor type and one size.....other than a big slow flash..”
4. “Low temperature transistors such as the ones they are describing cannot be as good as those made at high temperature.”
5. “Their number one argument for this technology is that there are no alignment issues. They bond the pair of wafers together and then remove most of the top wafer. True, there is no alignment required in this step, but then they must align thru the silicon to the underlying CMOS wafer for etching out the transistors. This does not appear to be a major advantage”
For all the latest on 3D IC Integration stay linked to Perspectives From the Leading Edge………
Posted by Philip Garrou on September 16, 2008 | Comments (0)
