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3D IC Integration: Rumors and Ruminations
February 8, 2008
Down here in Research Triangle Park NC it’s hard to believe that it’s early February. It’s been in the low 70’s which is about 25 degrees above normal. If this is an indication of global warming, we are all in trouble and I’ll be looking for land next summer in Maine......... I always did love Ogunquit. On the microelectronics front, nothing remains hotter than 3D.
For those looking for an equipment this auction announcement out there: http://www.thebranfordgroup.com/DNN3/Auction/CUBI2.aspx listed as “complete development facility closure”. Cubic Wafer has not updated their web page since Sept 2005......hummmm
Earlier in January In-Stat reported that the first product in the Intel Larrabee product family “...is targeting graphics, will bring together a new high-speed on-chip interconnect, LPIA processor core(s), graphics cores(s) and die stacking for cache memory, a first from Inel...”. Some, are interpreting this as Intel’s commercialization of their 3D integration technology using TSV. We know they said they were ready for this ( see Perspectives from the Leading Edge ....Intel announces "...we are ready" – Oct 29th 2007) My recent inquiries to Intel employees working in the 3D area have generated responses such as “...the company has requested that we do not comment about Larabee technology” We’ll all just have to ruminate on this until it becomes clearer.
If I was a betting man, I’d say that we see some of the first stacked memory in high end Samsung phones. Think about it....they've already shown us the stacked technology and they are a major player in the cell phone market....what better chance to test the waters for stacked memory....makes sense correct ??
Recall, way back in 2006 Samsung announced the company’s first 3-D prototypes based on its WSP ( wafer-level stack process). A 16-Gbit memory device composed of eight stacked, 50-micron thick , 2-Gbit NAND flash die which are a combined 0.56 mm in height was fabricated. The stacked device showed a 15 percent smaller footprint and is 30 percent thinner than an equivalent wire-bonded solution. WSP also reduced the length of the interconnects, resulting in an approximately 30 percent increase in performance due to reduced electrical resistance. Samsung’s WSP technology uses lasers to form the TSV which reportedly reduces production cost significantly as it eliminates the typical photolithography-related processes required for mask-layer patterning. The now famous photo and cross section have been shown many times in many places, but I’ll include it again here in case there are any readers who have not seen it.
Samsung 16Gb NAND stack with TSV
Since Samsung also has a 15 – 20% market share in the CIS market (CMOS Image Sensor) this also appears to be another no brainer. We already know that 3D CIS technology can make use of laser via formation ( see Perspectives from the Leading Edge “Imaging Chips with TSV Announced for Commercialization” – Oct 27th 2007 ) and Samsung has already shown they have such laser via processing available for their stacked memory. Although they have not yet discussed TSV for CIS, this certainly appears to be a logical baby step for them.
Highly placed managers and engineers in Samsung report that a complete information freeze on projects using 3D technology has been ordered from the very top. Anyone who can pry information loose on when they will commercialize is a better man than I. Another one that we’ll just have to ruminate on for awhile.
Both EVG ( see Perspectives from the Leading Edge EVG Discusses Status of 3D Integration” – Jan 20th 2008) and Suss indicate that their wafer bonding tools are selling well and point towards a post 2010 manufacturing boon for 3D integration.
Speaking of market timing, Jan Vardaman at TechSearch has finally released her long awaited 3D Market and technology study “Through Silicon Via Technology: The Ultimate Market for 3D Interconnect” (I contributed heavily to the technical section – full disclosure thing) so there are now two sets of marketing data to compare. The Yole group has made several public presentations of their data. ( see Perspectives from the Leading Edge “Discussions in the Valley” – Nov 4th 2007) Yole projects that 5MM 3D wafers will be manufactured in 2012 which will include 63% of the image sensor market, 20% of the DRAM market and 30% of the flash market. Since Jan has not publicly divulged her numbers yet, I cannot print them here, but lets just say they are slower to develop, due, she feels, to the fact that there are still issues to be addressed in market segments outside of image sensors for which she is very aggressive.
Ted Tessier is this years General Chair for the IMAPS Device Packaging Conference in Scottsdale. There will be five full sessions of 3D technology and it appears that all the major players will once again be represented. ……….. for all the latest information on 3D integration stay linked to Perspectives from the Leading Edge
Posted by Philip Garrou on February 8, 2008 | Comments (0)
