Philip Garrou

More 3D IC Integration from Ft McDowell
March 30, 2008

This week I’m continuing to share information from the recent IMAPS Device Pkging meeting that was held on the Ft. McDowell reservation north of Scottsdale AZ. Must be because of the time I grew up....but as I type Ft McDowell my mind begins to wander to those great late 1950s westerns .... MGM proudly presents ”Ft McDowell” starring John Wayne, Gabby Hayes and Rita Haywerth. Anyway back to technology......

IMEC

Before I get to presentations and rumors from the meeting I’d like to share with you a new process variation that has been developed by Eric Beyne and the other 3D researchers at IMEC. As you can see from the figure below they first bond the wafer face down to a carrier and, after thinning to 50 microns, cut an annular via down from the backside of the wafer stopping on the oxide layer under the die pads. The annular via is not unusual...we have seen this from the likes of IBM, Elpida and others, and is used to speed up the DRIE process. What IMEC does next is quite unique. They fill this “doughnut ring” with a polymer like BCB and then DRIE or wet etch the center Si column to leave a polymer insulated via for metal conductor filling. Thus, they are able to use polymer materials that could not normally be used because they can not be deposited conformally in a high aspect ratio via. At first glance this looks like an extra process step to create a via, but it just might have some utility for applications where processing temperatures have to be kept to a minimum - for example future DRAM processing. Materials like BCB can be cured as low as 200 – 210 C whereas TEOS deposition is normally 300 C (although there are indications that low temp TEOS processes are being developed (see Perspectives from the Leading Edge - “...Practitioners assemble at Ft McDowell” - 3-23-08) . Note that IMEC has filed for patents on this process sequence.

Tezzaron

At the meeting, Bob Patti, one of the earliest supporters and practitioners of 3D IC integration for memory products, had the audience paying attention. Previous presentations by Tezzaron described their two processes: “SuperVias™” - a post back end of line process which used copper for conductor fill (ca. 4-5 um dia vias) and did Cu-Cu fusion bonding before thinning to avoid using handle wafers and “SuperContacts™” a W (1.2 um dia) based vias first technology which again bonds before thinning to avoid the use of handle wafers. Bob has now announced that they are no longer supplying the SuperVias because “...it is a more difficult process and is really unneeded” They are now exclusively running W contacts at 1.2um for 200 mm and 1.6 um for 300 mm wafers. They are working towards 0.8 um W TSV at 1.76 um pitch for their next memory devices. Bob also warns that “...there are also some issues with Cu TSV and transistor performance at the deeper sub micron geometries ! “

Next Bob indicated that Tezzaron is in the process of bringing up two more fabs (they had previously announced their supply arrangement with Chartered) on their SuperContacts process.

Completely unsubstantiated rumors abound at the meeting that one of the foundries was TSMC and that TSMC and ASE have an agreement in place to work together on 3D IC Integration technology where TSMC fabricates TSV during the foundry process and ASE is ready, willing and able to do the rest of the process for customers. Again, no one is willing to substantiate any part of these rumors.....but they sure do make sense.

Panel Session

I led off the panel session with some introductory remarks emphasizing my theme of "evolution NOT revolution" that you saw a few weeks ago (Perspectives from the Leading Edge – “...Evolution or Revolution” 3-16-08) and was supported by the rest of the panel in this view (Vardaman – TechSearch, Schaper – Arkansas, Berry – Amkor, Lu – RPI, Flynn Carson – STATSChipPAC ). One thing that appears to have changed in the last 6 – 12 months is that the package and assembly houses like Amkor and STATS now appear to be on the bandwagon that, for the most part, the fabs will be doing the TSV and they will be offering the rest of the process. This just makes too much sense for it to go any other way.

Updated Marketing Info

Eric Mounier from Yole updated their market findings in the area of 3D integration. Since the RTI 3D IC meeting in the fall of 2007, Yole has significantly increased their penetration of TSV for CMOS Image Sensors (CIS) , reversed itself on the previously announced FLASH before DRAM sequence and redone their total market penetration numbers as shown below. Although they removed the labeling of the Y axis (# wafers / year) we can look at the blowout for 2008 which is labeled 200K wafers and by extrapolation determine that each tick mark is 2MM wafers. Thus, they are predicting just under 4MM wafers in 2011 and just under 10 MM wafers in 2013. I think the market penetration for DRAM is still much to aggressive, but time will tell.

Next week we will continue to cover technical highlights from the IMAPS meeting until then stay linked to Perspectives From the Leading Edge.....................................

Posted by Philip Garrou on March 30, 2008 | Comments (0)