Philip Garrou

3D Integration invades Whitefish Montana
September 7, 2007

The Peaks in Packaging Conference held in Whitefish Montana has traditionally covered bumping and wafer level packaging. This year the theme has switched and the agenda has overwhelmingly been concerned with 3D integration. Semitool, the host of this conference, is a member of the EMC-3D consortium which I covered in detail in my last blog.

The presentations the last few days have run the gamut from EMC-3D members detailing their function in the consortium to new and novel materials and processes being proposed for inclusion in the 3D technology tool box.

I gave the audience a introductory presentation trying to summarize some definitions that we all need to adhere to. I thought it would be good to present some of these here for your comments. Experts such as Bob Patti from Tezzaron, Peter Ramm from Fraunhofer Munich, Fred Roozeboom from NXP, David Henry from CEA Leti and many others from around the world were consulted and are in agreement with these definitions.

The TSV can be fabricated at 3 points in a process which are:

• FEOL
• BEOL
• After IC fabrication

BEOL and FEOL TSV are formed in the fab by the IC manufacturer. The FEOL TSV as formed before the devices are fabricated. The only material that can survive the subsequent device processing temperature is poly silicon. The BEOL TSV are formed after the devices and can be made of W or Cu. The post BEOL TSV must have exclusion zones built into their designs so that the TSV can be etched into the chips post IC fabrication. These TSV can be made of W or Cu.

Another important classification is “vias first” vs “vias last”.

• vias first indicates that the TSV are formed before wafer to wafer bonding
• “vias last” indicates that TSV are formed after bonding of the wafers

TSV that are put into the IC after the IC fabrication is complete, but before the wafers are bonded should still be defined as “vias first”.

Another area of some confusion is the handle or carrier wafer. The carrier wafer serves two functions. It is:

• Used to support the substrate during the thinning process
• Used to transfer layers to the 3D stack

TSV are formed either:

• Before attachment to the handle wafer (vias first)
• After attachment of the thinned layer to the 3D stack (vias last)

Thinning is done either:

• After attachment to the handle wafer (before bonding)
• After face-to-face bonding to the 3D stack (no handle)

We hope these definitions will be of some help in discussing this exciting area of 3D integration. More coverage of the Peaks meeting in Whitefish will come shortly…………………….

Posted by Philip Garrou on September 7, 2007 | Comments (0)