Philip Garrou

SMTA 3D Meeting in Research Triangle PArk
May 10, 2008

It must be nice for those of you living in the Bay area where conferences on every microelectronic topic imaginable are held on an almost weekly basis. Not so for those of us living in the rest of the country. A few weeks ago SMTA held their second 3D, SiP Conference in RTPNC, right here in my back yard. I thought I’d share some of the interesting things that were presented.

Biao Cai of IBM gave a presentation on trends in DRAM packaging for Servers. His key points were:

• Memory capacity growing at minimum 2X per generation
• Memory performance growing at minimum 3X every 3 years
• DRAM technology scaling approaching fundamental limits
• System volumetric space allocation for memory approaching physical limit

He pointed out that 3D with TSV technology is under evaluation for 2012-BEYOND for DDR3~DDR4. We are in agreement.

Ritwik Chatterjee has moved from Motorola to good friend Rao Tummala’s Ga. Tech Packaging Center to lead the 3D program there, which they call “All Silicon System Module” (shown in the figure below). Fraunhofer IZM Berlin and Kaist are co-sponsoring this proposed consortium. Further details can be found on their web site.

Paul Sibelrud of Semitool gave the EMC-3D consortium pitch. For details see past blogs such as “3D Equipment and Material Vendors Consortium” – Aug 26th 2007 in Perspectives from the Leading Edge. Paul pointed out correctly that Cost of ownership (COO) is the ultimate driver for this or any other technology.

EMC-3D is considering both vias first and vias last process flows but is starting with a vias last approach. ( Readers of this blog know that I favor the FEOL vias first, from the fab, business model)

Using the Sematech COO cost model EMC-3D claims that 3D IC integration will be down to $162 / wafer sometime in 2009. I think this is aggressive, but hope it is correct.

                          Year                          capital (MM$)           COO ($/wafer)

                          2008                                38                               204

                          2009 (expected)           32                               162

For all the latest on 3D IC Integration stay linked to Perspectives from the Leading Edge............................

Posted by Philip Garrou on May 10, 2008 | Comments (0)