Philip Garrou

3D Integration - Sources
August 5, 2007

3D INTEGRATION is the latest super hot topic on absolutely everyone’s radar screen. You might be interested in where you can catch up on the literature in this area. In the last few years I have covered this topic a number of times for SI including:

Feb 2005 “Future IC’s go Vertical”

Oct 2006 “Wafer Level 3D Integration Moving Forward”

April 2007 “Posturing and Positioning in 3-D ICs”

IMAPS has had several tracks of papers at their 2006 and 2007 Int. Device Packaging Conferences which were held in Phoenix AZ.

The “3D architectures for Semiconductor Integration and Packaging” Conference held yearly since 2005 by RTI International has focused solely on 3D integration and is attended by all of the worlds experts.

The IEEE Components Packaging and Manufacturing Technologies (CPMT) divisions premier conference, the ECTC (Electronic Component Technology Conference), had 3 sessions this year in Reno focused on 3D.

Major breakthroughs by Intel, Samsung and NEC have been disclosed at the IEEE IEDM conferences the past two years. The IEEE IITC conference looks like it is also beginning to focus in on the 3D technology and applications space.

The Materials Research Society (MRS) had two day track devoted to “enabling 3D technologies” at its fall Boston meeting in 2006. (see MRS Symposium Proceedings volume 970 “Enabling Technologies for 3D Integration”, Ed. C. Bower, P. Garrou, P. Ramm, K. Takahashi).

There is a lot more information also on the way:

TechSearch Inc. consulting is getting ready to release the 2nd of their 3D technology and market reports entitled “3D Interconnect with TSV Technology”.

This spring will bring the publication of the Wiley VCH title “3D Integration for Integrated Circuits” edited by myself, Peter Ramm and Chris Bower.

A little birdie has told me that IEEE CPMT is in the process of forming a 3D Integration technical committee which will be responsible for initiating an IEEE conference solely focused on 3D integration, possibly as early as 2008.

Equipment suppliers and consortia:

Semitool, EVG and several other partners have initiated the consortium EMC-3D.

Word is Suss, Nexx and STS are about to announce a similar group.

The latest team to step forward is the partnership of Rao Tumala’s Georgia Tech PRC joining with RTI’s 3D research team to address 3D silicon stack and substrate technologies.

Last, but not least, Sematech who launched its 3D program in early 2005 and claims a comprehensive cost-model and a draft of a 3D roadmap for the International Technology Roadmap for Semiconductors (ITRS), has opened the doors to new members to join its 3D Interconnect program. SEMATECH future work will focus on development of 3D infrastructure, materials, unit processes, integration, and reliability. "3D is a critical program for the semiconductor industry, and we're building the critical mass to help drive it," said Sitaram Arkalgud, director of SEMATECH's interconnect division.

So, catch up on your reading and we’ll be discussing where all this is going in future blogs................

Posted by Philip Garrou on August 5, 2007 | Comments (0)