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Keepin' it Cool in the Dog Days of Summer
September 1, 2008
Those of you that were alive, as I was, before central air became a standard item in every home and automobile, recall the term “dog days of summer”. No matter how hard you tried, you just couldn’t cool down because you could only get so much relief sitting in front of a fan blowing hot air at you !
As we have discussed before, cooling has always been a worry of those ordained with bringing 3D IC based products into manufacturing. As we have looked at the likely timeline for application introductions, early applications have all had one thing in common – they were applications which minimized possible thermal issues. For instance, see the very informative article by Pat Morrow, Byran Black and their Intel co-workers [ “Enabling Technologies for 3-D Integration” MRS Symp Proceed V. 970; C. Bower, P. Garrou, P. Ramm, K. Takahashi Eds. p. 91-102]. For the 3D microprocessor floor plan that is discussed, they achieve an average 66% reduction in average bus power, due to reduced bus activity, and thus the peak temperature only increases 1.92 °C for memory on logic stacking of DRAM on a 92W microprocessor. In a recent DRAM stacking study by Loh at GaTech [ 3D Stacked Memory Architectures for Multicore Processors”, [IEEE Computer Architecture Conf, June 2008] they concluded that the worst case temperature across the entire 3D stack is well within the maximum thermal limit specified by Samsung.
We all do know, however, that if 3D-IC is to become the major mainstream technology that most of us think it will, it must face the “thermal dragon” sooner or later. The good news is that there are technologists out there “working this issue”. The hope is that low cost solutions will be ready on time.
In the past we have looked at startup Nextreme Thermals “copper pillar bump” as a way to potentially alleviate thermal hot spots. [ PFTLE, “Whats the Capitol of NY State? “, 10/14/2007] In this weeks blog I’ll take a look at some recent thermal studies on liquid cooling options.
Microchannel cooling was first demonstrated in 1981 by Tuckerman and Pease. More recently Koo [2005, ASME J Heat Transfer], proposed the use of microchannel cooling for 3D structures as shown in the figure below.
IBM Zurich
At this summers IEEE I- Therm Conf Thomas Brunschwiler and his collegues at IBM Zurich, working with Herb Reichl’s team at the Fraunhofer IZM (Berlin), presented the paper "Forced convective interlayer cooling in vertically integrated packages"
They described integrating a cooling system which forced liquid into 100 micron cooling channel structures between the individual chip layers in their thermal test vehicles. The cooling layer consisted of 10,000 hermetically sealed TSV per cm2. They were able to extrapolate cooling performance of 180 W/cm2 per layer for a stack with a typical footprint of 4 sq cm. The IBM / Fraunhofer IZM team indicated they are working to optimize this cooling technology for smaller chip dimensions and more interconnects. They are also investigating additional structures for hotspot cooling.
GaTech
At the recent IEEE IITC conference earlier this summer Jim Meindl’s group at GA Tech described similar liquid cooling technology for 3D stacks in their work “A 3D-IC Technology with Integrated Microchannel Cooling”. Their process flow is shown in the fig below. After fabrication of the chip including the electrical TSVs (steps 1 & 2) bosch etching is used to fabricate fluidic TSVs and microchannels (step 3). Next, a sacrificial polymer material is spun on/into the microchannels and polished (step 4). A permanent polymer (Avatrel) is next spun-on, patterned and cured to form a cover for the microchannels and fluidic TSVs and the sacrificial material is decomposed by heating to 260°C (step 5).
The assembly technology is outlined the following asteps. After solder bumping, fluidic pipes are fabricated with a polymer such as Avatrel for the top chip in a two chip 3D stack. The bottom chip in the two chip 3D stack is first assembled onto the substrate with a flip-chip bonder. Following this, the top chip in the 3D stack is assembled onto the bottom chip as shown in step (3). Underfill is dispensed to seal fluidic pipes and control co-efficient of thermal expansion mismatches between the chip and the substrate.
One always worries about pressure drop when looking as such small cooling channels. The work in this study reveal that fluidic TSVs and pipes consume minimal surface area for a two-chip microchannel cooled 3D integrated circuit, and at the same time have negligible pressure drop through them. This is largely because the total length of fluidic vias and pipes is only 0.9mm while the length of microchannels is as high as 10mm.
Freescale – Austin
At the same IITC meeting Bob Jones Freescale group in Austin presented their study “Thermal Modeling and Design of 3D Integrated Circuits”. An analytical model for temperature distribution in a multi-die stack with multiple heat sources was developed. The analytical model was used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. I’ll let you go through the detailed modeling calculations yourself, but I’ll leave you with the conclusions which are that the thermal resistances within a 3D structure are expected to be much smaller than those outside, including the heat sink and package. As a result, they conclude that thermal optimization of 3D ICs needs to be driven by reduction in thermal resistance of the heat sink and package, and not of the 3D IC itself. An interesting thermal challenge surrounding 3D technology is that 3D stacking, by causing a beneficial volumetric reduction in the footprint area, will as a consequence create the necessity of a quicker introduction of cooling technologies and the integration of electrical and thermal design processes for 3D integrated microelectronics.
CALC – Univ Maryland
Finally, Avi Bar-Cohen ( CALC - U Maryland) recently presented a review of the status of 3D Immersion cooling entitled “Pool and Flow Boiling in Narrow Gaps – Application to 3D Chip Stacks”, as the keynote Lecture at Eurotherm 2008. This thorough review of immersion cooling is way to detailed to summarize here, so I suggest you get a copy of it for yourself if your wanting to catch up on the latest 3D thermal technology options. .
Most of us can probably envision liquid cooling for server applications, but the real crystal ball question is “Will liquid cooling ever be used for stacked 3D chips in portable products ??” ......your opinions are welcomed
Taiwan 3D workshop
Before I close I want to point out that there will be a 3D-IC workshop on October 9th in Taiwan focused on EDA tool and design technology for 3D-IC. This event is sponsored by the newly established Taiwan-based 3D-IC Alliance. More on that in the future...................
For all the latest on 3D IC Integration stay linked to Perspectives From the Leading Edge (PFTLE).............................
Posted by Philip Garrou on September 1, 2008 | Comments (0)
