Philip Garrou

October in Munich
December 16, 2007

If my title is “October in Munich” I must be getting ready to talk about my experiences at Octoberfest – correct ? Well no.....I’m going to talk about the second biggest thing happening in Munich this past October which was the International Workshop on 3D System Integration. Peter Ramm and Juergen Wolf of Fraunhofer IZM Munich and Berlin respectively put together a program covering the various approaches to 3D packaging and 3D IC Integration, which as you know has been a focus of this “Perspectives From the Leading Edge” blog. While I had t cancel my trip there due to a bad back, there were several noteworthy presentations given at this meeting that I’d like to comment on and suggest that you try to obtain copies of ( I’m sure the meeting CDs are available for a price).

When it comes to the details about making TSV and stacking ICs into 3D integrated devices, Armin Klumpp is the “ 3D Scientist Extraordinaire” at the Munich Fraunhofer known for its vertical 3D integration. IZM-Munich, as you may recall helped develop the Infineon 3D stacking technology several years ago. While they have developed several process scenarios, they have concentrated on the use of high aspect ratio TSV and bonding by “solid-liquid interdiffusion” ( or SOLID as they call it) with tin capped copper pillars. While the diameter / pitch on lead containing and lead free leading edge “micro bumps” is reaching 50 / 100, the fluxless SOLID process is limited in pitch only by the bonder alignment accuracy. A comparison of BGA vs SOLID is shown below.

I would be remiss if I did not mention that at the last ECTC meeting (2007) in Reno there were rumors that such interdiffusion bonding technology was having trouble passing the drop test. Something to check out more thoroughly before committing to this as a bonding technology.

Some interesting 3D packaging technologies were presented by DeBaets and Beyne from IMEC in Belgium. Their look at laminate 3D packaging solutions included embedded die stacking. Their Euro program studying this area is called “Hiding Dies”. As you can see from the figure below, they place the thinned die on the PWB double sided core board before laminating on the resin coated copper foil [RCC]. They then access the chip pads by laser ablating vias down through the RCC. This process can be repeated several times to laminate chips INTO both sides of the board. Theoretically this allows you to combine different size dies. Technology such as this always looks good as power point presentations but what we always want to know is – what are the issues ??? We were not disappointed in this case because DeBaets went into detail about the processing issues such as :

• the lamination pressure is important since the die bonding surface is not flat
• the second chip tends to “warp” due to the thickness of the chip below it and uneven copper distribution under the chip
• the finest pitch they were able to realize was contacting to 60 um pads on 100 um pitch
• more advanced techniques will be necessary to improve yield and reliability

Finally Bob Darveaux of Amkor gave a nice update on how Amkor is getting ready for all types of 3D technology

Thinning - they are examining several wafer support systems which will allow them to thin down to 30 um by the end of 2008. Edge trimming will be required

Dicing – looking at laser sawing to reduce the mechanical stress during sawing

WB stacking - looking at 50 um ultra low loop height technology and confirmed the feasibility for 0.8 mil wire

Chip-on-chip – looking at F2F chip on chip technology to allow embedded DRAM to be removed from logic die but maintain high speed and high bandwidth

TSV – they think that OSATs will develop front side or backside vias last technologies to take care of chips that did not have TSVB inserted into the FAB process.

As the holiday season approaches stay linked to "Perspectives from the Leading Edge".................

Posted by Philip Garrou on December 16, 2007 | Comments (0)